Senior Digital VLSI Design Engineer (Synthesis/DFT)

TL;DR

Senior Digital VLSI Design Engineer (Synthesis/DFT): Defining and enforcing synchronization strategies for high-speed complex IPs with an accent on synthesis, DFT, and CDC/RDC sign-off. Focus on establishing rigorous constraints, ensuring zero-defect silicon, and mentoring the design team on best practices for advanced process nodes.

Location: Must be based in Fort Collins, Colorado, USA

Salary: $121,900 – $195,000

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Define and enforce synchronization strategies across complex, multi-clock domains.
• Own the constraint creation process for synthesis and full-chip CDC/RDC methodology.
• Collaborate with Architecture and Chip Lead teams to review testability, DFT, clocking, and reset architectures.
• Identify potential metastability or reset-glitch issues early in the design cycle.
• Mentor the broader design team on synthesis, DFT, and CDC/RDC best practices.
• Drive automated flows to streamline sign-off for multi-site global teams.

Requirements

• BSEE degree required (MSEE/PHD preferred).
• 8+ years of related experience in digital VLSI design.
• Deep expertise in Synthesis, DFT, CDC, and RDC sign-off.
• Mastery of structural and functional verification tools such as SpyGlass, Lint, JasperGold, or Meridian.
• Experience with high-speed interfaces like SerDes, DDR, or HBM.
• Must be authorized to work in the USA.

Culture & Benefits

• Competitive base salary with discretionary annual bonus.
• New hire equity grant and annual equity awards.
• Comprehensive medical, dental, and vision insurance plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Paid holidays, sick leave, and vacation time.