Digital Design RTL Engineer (SystemVerilog)

Location: Fort Collins, Colorado, USA; onsite at 4380 Ziegler Road

Annual base salary: USD 121,900–195,000, plus discretionary annual bonus and equity awards.

Company

hirify.global develops semiconductor and technology solutions.

What you will do

• Take digital designs from initial specification through timing closure and physical design hand-off.
• Develop high-quality SystemVerilog RTL for advanced process nodes at 5nm and below.
• Optimize power, performance, and area (PPA), including low-power design techniques.
• Perform clock domain crossing and reset domain crossing analysis.
• Collaborate with Architecture, Verification, and Physical Design teams to mitigate risks and deliver project milestones on schedule.

Requirements

• High proficiency in SystemVerilog and RTL design.
• 8+ years of industry experience.
• Bachelor of Science in Electrical Engineering required; a master's degree or PhD preferred.
• Experience with SoC integration and preferably LPDDR5/6, DDR4/5, high-speed SerDes, or HBM protocols.
• Ability to work onsite in Fort Collins, Colorado, USA.

Culture & Benefits

• High-autonomy role with cross-functional collaboration.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Employee Assistance Program, paid holidays, paid sick leave, and vacation time.
• Paid family leave and other leave benefits in accordance with applicable laws.