Digital Design RTL Engineer (SoC)

TL;DR

Digital Design RTL Engineer (SoC): Developing high-quality SystemVerilog RTL for advanced process nodes with an accent on PPA optimization, CDC/RDC analysis, and low-power design. Focus on collaborating with architecture and physical design teams to drive designs from specification to timing closure.

Location: Must be based in Fort Collins, Colorado, USA

Salary: $121,900 – $195,000

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Take designs from initial specification through to timing closure and physical design hand-off.
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams.
• Mitigate project risks and ensure milestones are met on schedule.
• Develop high-quality SystemVerilog RTL for advanced process nodes (5nm and below).
• Perform PPA optimization and clock domain crossing (CDC) analysis.

Requirements

• Must be based in or able to work from Fort Collins, Colorado.
• BSEE degree required (MSEE/PhD preferred).
• 8+ years of industry experience in SoC integration.
• High proficiency in SystemVerilog.
• Deep understanding of low-power design techniques and high-speed protocols (LPDDR, DDR, SerDes, or HBM).

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and annual equity awards.
• Discretionary annual bonus eligibility.
• Paid holidays, sick leave, and vacation time.