Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Зарплата и рынок
Мало
$110к-176к/год
$140к$160кмедиана$190к
По похожим ролям (50) ~ $160к/год
На СНГ рынке: $1.9к/мес ($1.8к - $3к)
55
Средняя вакансия
развернуть
Роль четко определена с ясными обязанностями, но зарплата значительно ниже рыночных стандартов, что может снизить ее привлекательность.
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Низкая зарплатаЧеткое определение ролиСильная компания
Оценка от Hirify AI
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
Analog & RF IC Senior Layout Engineer (Analog/RF ICs and FinFET): Creating DRC/LVS-clean layouts for high-speed custom analog and digital IP blocks across advanced technology nodes with an accent on floorplanning, precision device matching, and critical-net routing. Focus on full-cycle ownership from initial floorplanning through tape-out and sign-off, solving complex parasitic and high-frequency layout challenges, and integrating top-level silicon designs.
Location: Irvine, California, USA; onsite at Alton Parkway Building 2
Annual base salary: USD 109,700–175,500, plus discretionary annual bonus and equity awards.
Company
hirify.global develops high-tech hardware and silicon products, including wireless, wireline, and AI hardware.
What you will do
Translate circuit schematics into DRC/LVS-clean layouts for critical custom IP blocks.
Collaborate with senior designers on floorplanning, power and ground architecture, and precision device matching.
Use Cadence Virtuoso, Virtuoso VXL, and Mentor Calibre for high-speed custom circuit layout and verification.
Own custom top-level and IP blocks from initial floorplanning through final tape-out and sign-off.
Route critical nets, match devices, assess schedules, and support top-level integration for high-frequency silicon designs.
Requirements
Extensive experience laying out high-speed custom analog and digital circuits, such as TX, RX, SerDes, and PLLs.
Deep familiarity with the Cadence Virtuoso tool suite, including the Virtuoso VXL layout suite, and Mentor Calibre verification.
Proven design and layout experience in advanced FinFET technology nodes.
Thorough understanding of layout fundamentals and a track record of solving complex circuit layout challenges.
BS degree in Electrical Engineering or a related field with 8+ years of related experience, or MS degree in Electrical Engineering or a related field with 6+ years of related experience.
Culture & Benefits
Close collaboration with experienced analog, RF, and circuit design engineers.
Work on advanced silicon involving physics, parasitic, and high-frequency design challenges.
Medical, dental, and vision plans.
401(k) participation with company matching, ESPP, and EAP.
Company-paid holidays, paid sick leave, vacation time, and applicable paid family leave.
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