Principal IC Digital Design Engineer (ASIC)

TL;DR

Principal IC Digital Design Engineer (ASIC): Designing high-performance connectivity silicon for AI scale data centers with an accent on high-speed datapaths and DSP-driven processing engines. Focus on RTL development, ASIC front-end design flows, and ensuring ultra-high bandwidth and low latency data movement.

Location: Irvine, CA. Must be eligible to access export-controlled information under U.S. law.

Salary: $151,000 - $223,440 per annum

Company

hirify.global provides semiconductor solutions that serve as the essential building blocks of data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Collaborate with systems and architecture teams to define SoC-level specifications, including performance, power, and area requirements.
• Translate product and protocol requirements into detailed micro-architecture specifications for DSP pipelines and high-speed datapaths.
• Own RTL development using SystemVerilog, delivering high-quality synthesizable code.
• Drive the full ASIC front-end design flow, including lint, CDC/RDC, synthesis, and timing constraint development.
• Partner with STA and PNR teams to support timing closure and design optimizations on advanced process nodes.
• Lead the integration of digital logic into subsystems and support pre- and post-silicon validation and debug.

Requirements

• 12+ years of industry experience in digital ASIC design for networking or data-center connectivity.
• Strong background in high-performance DSP and high-speed datapath design.
• Familiarity with Ethernet protocols and networking standards (MAC, PCS framing).
• Proficiency with front-end design flows, including synthesis, STA, and power optimization.
• Experience with advanced process nodes (5nm, 3nm).
• Eligibility to access export-controlled information as defined under U.S. law.

Nice to have

• Experience with advanced high-speed DSP algorithm implementation (FFE, DFE, CTLE).
• Experience with FEC architectures such as LDPC, RS, or BCH.
• Previous PHY design experience, including PMA-level DSP pipelines and SerDes-adjacent logic.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate contributions.