Design Verification Engineer (Silicon)

TL;DR

Design Verification Engineer (Silicon): Verification of next-generation interconnect and chassis IPs for SoC and platform products with an accent on testbench development and functional coverage. Focus on building constrained-random tests, root-causing simulation failures, and integrating AI-assisted development tools.

Location: On-site in Santa Clara, California, US. This position is not eligible for immigration sponsorship.

Salary: $105,650 – $149,150 USD

Company

A global leader in semiconductor design and manufacturing, focusing on scalable engineering solutions for product and foundry businesses.

What you will do

• Develop testbench components, constrained-random stimulus, and functional checkers for interconnect and chassis IP.
• Write, run, and debug simulation tests, analyzing and root-causing failures to closure.
• Contribute to functional coverage plans, coverage closure analysis, and regression triage.
• Participate in spec reviews, design discussions, and bug triage across architecture and software boundaries.
• Implement AI-assisted coding and debugging tools to automate workflows and increase productivity.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or Computer Science.
• Strong foundation in logic design and digital circuits, with the ability to reason about RTL.
• Proficiency in at least one of C/C++, Python, or SystemVerilog.
• Knowledge of computer architecture, operating systems, or VLSI design.
• Must be eligible to work in the US without immigration sponsorship.
• Experience using AI coding assistants as a regular productivity tool.

Nice to have

• Experience with hardware verification, FPGA design, or RTL simulation (ModelSim, VCS, Questa).
• Familiarity with UVM concepts or assertion-based verification.
• Knowledge of standard bus protocols (AXI, AHB, PCIe) or memory hierarchy.
• Comfort working in Linux environments and using git version control.

Culture & Benefits

• Competitive pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Opportunity to work with next-generation interconnect and chassis IPs.
• Supportive environment for New College Graduates to ramp up technical depth.