Physical Design Engineer (Semiconductors)

TL;DR

Physical Design Engineer (Semiconductors): Implementing custom IP and SoC designs from RTL to GDS for data center products with an accent on power, frequency, and area optimization. Focus on executing synthesis, place and route, and static timing analysis to ensure manufacturable silicon solutions.

Location: On-site presence required in Beaver Brook, MA or Phoenix, AZ, USA

Salary: $91,150 - $149,150 USD

Company

hirify.global is a global leader in semiconductor innovation, designing and manufacturing silicon products that power digital lives and data centers.

What you will do

• Perform physical design implementation of custom IP and SoC designs from RTL to GDS.
• Execute synthesis, place and route, clock tree synthesis, and floor planning.
• Conduct power and noise analysis, reliability verification, and optimization.
• Verify and sign off designs using formal equivalence, layout verification, and dynamic power integrity checks.
• Optimize product-level parameters such as power, performance, and area (PPA) using EDA tools.
• Contribute to the development of physical design methodologies and automation flows.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field.
• 1+ years of experience in physical design (or a Master's degree with 0 years of experience).
• Experience with integrated circuit design tools, including logic synthesis and static timing analysis.
• Knowledge of RTL design and timing closure processes.
• Experience with scripting in TCL.

Culture & Benefits

• Competitive total compensation package including pay and stock bonuses.
• Comprehensive benefit programs covering health, retirement, and vacation.
• Opportunity to work within the Data Center Group (DCG) on AI-accelerated systems and Xeon-based solutions.
• Collaborative environment focused on bold invention and relentless innovation.