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updated 14 days ago

Senior Staff Physical Verification CAD Engineer (EDA)

127 630 - 191 200$
Work type
fulltime
Grade
senior
English
b2
Country
US
This vacancy is from Hirify.Global listVacancy from Hirify Global, list of international tech companies
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Job description

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TL;DR
Senior Staff Physical Verification CAD Engineer (EDA): Developing and supporting CAD and EDA flows for semiconductor physical verification, SoC integration, and tape-out with an accent on DRC/LVS debugging, tool integration, and design automation. Focus on building run sets and validation procedures, optimizing physical verification methodologies, and resolving complex tool and design-flow issues across foundry and cross-functional engineering teams.

Location: Santa Clara, California, United States

Salary: $127,630–$191,200 per year

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, and carrier data infrastructure.

What you will do

  • Develop run sets and automate physical verification flows for semiconductor design and manufacturing.
  • Support Calibre and ICV, including DRC and LVS debugging, tape-out activities, and foundry interface work.
  • Develop and integrate CAD and EDA tools and methodologies for digital and analog IC design, verification, and physical implementation.
  • Define and optimize design flows, design rule decks, layout migration, and SoC integration processes.
  • Evaluate, monitor, and improve third-party EDA tools, libraries, IPs, and overall tool performance.
  • Collaborate with foundry, design, layout, and software engineering teams while providing technical guidance and training.

Requirements

  • Bachelor’s degree with 5–10 years of related experience, or a master’s degree/PhD with 3–5 years of experience; equivalent professional experience may substitute for a degree.
  • Experience developing and supporting CAD and EDA tools, preferably in the semiconductor industry.
  • Hands-on knowledge of EDA tools and IC design flows, including Cadence, Synopsys, Mentor Graphics, Tcl, Perl, and Python.
  • Synopsys ICV is required; Mentor Calibre SVRF/TVF is preferred.
  • Understanding of the complete IC design flow from RTL, synthesis, and simulation through place and route, timing analysis, and physical verification.
  • Experience leading initiatives, providing technical guidance, mentoring junior engineers, and solving complex design or tool issues.

Culture & Benefits

  • Benefits support financial well-being, family support, mental health, physical health, and recognition.
  • Employee stock purchase plan with a two-year lookback.
  • Family support programs and mental health resources.
  • Recognition and service awards for contributions and milestones.
  • Access to export-controlled technology may require eligibility under U.S. export control laws and an export license review.

Hiring process

  • Interviews assess individual experience, thought process, and communication skills in real time.
  • AI tools, transcription apps, automated note-taking bots, and real-time answer generators are not permitted during interviews.

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