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6 часов назад

Staff DFT Engineer (Semiconductor)

113 920 - 170 600$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
c1
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Staff DFT Engineer (Semiconductor): Implementing and verifying DFT architectures for high-performance data center and AI infrastructure with an accent on MBIST, BISR, and IJTAG. Focus on end-to-end ownership of DFT insertion, DRC closure, and post-silicon debug to ensure robust test coverage.

Location: Santa Clara, CA

Salary: $113,920 - $170,600 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

  • Perform hands-on DFT implementation, including MBIST, BISR, Boundary Scan (IEEE 1149.x), and IJTAG (IEEE 1687) insertion.
  • Execute DFT verification, debug, and DRC closure using Siemens Tessent and SpyGlass DFT/RTL checks.
  • Generate, simulate, and debug MBIST and logic ATPG patterns to drive test coverage closure.
  • Develop and validate DFT timing constraints for scan, BIST, and test modes.
  • Automate DFT insertion and analysis flows using TCL scripts.
  • Collaborate with RTL, Physical Design, and ATE teams to support pre-silicon signoff and post-silicon pattern bring-up.

Requirements

  • Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or related fields.
  • 5+ years of hands-on DFT implementation experience.
  • Strong proficiency with Siemens Tessent (MBIST/BISR, Boundary Scan, IJTAG, ATPG).
  • Strong TCL scripting skills for DFT automation.
  • Experience with the full DFT lifecycle from RTL/netlist through silicon debug.
  • Must be eligible to access export-controlled information as defined under U.S. export control laws.

Nice to have

  • Experience in MBIST coverage improvement and repair efficiency optimization.
  • Post-silicon experience including pattern bring-up, tester conversion, and silicon characterization.
  • Exposure to mixed-signal or SERDES DFT, such as IOBIST or loopback testing.

Culture & Benefits

  • Employee stock purchase plan with a 2-year look back.
  • Comprehensive family support programs to balance work and home life.
  • Robust mental and physical health resources.
  • Recognition and service awards for contributions and milestones.

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