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Physical Design Engineer II (Semiconductor)

Формат работы
onsite
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Physical Design Engineer II (Semiconductor) (ASIC/EDA): Executing synthesis, place-and-route, static timing analysis, and physical verification for assigned ASIC partitions with an accent on timing convergence, EM/IR closure, low-power design, and sub-7nm implementation. Focus on resolving signoff and flow issues, refining Cadence/Synopsys methodologies, and developing TCL-based implementation flows.

Location: Complete on-site in San Jose, California, with travel to an Arrow client office as requested by client leadership

Competitive financial compensation and benefits package

Company

eInfochips, an hirify.global company, provides product engineering and semiconductor design services across connected products and multiple technology verticals.

What you will do

  • Execute synthesis, place-and-route, and static timing analysis for assigned ASIC partitions.
  • Resolve implementation and signoff issues with architects, RTL designers, DFT engineers, and methodology owners.
  • Drive EM/IR closure, logical equivalence checking, and physical verification signoff.
  • Identify physical design challenges and improve iteration and convergence.
  • Refine synthesis, PnR, EMIR, PDN, and LEC methodologies.
  • Troubleshoot implementation flows and coordinate with EDA vendors.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
  • 7+ years of hands-on physical design and implementation experience.
  • Experience with synthesis, PnR, timing convergence, and physical verification.
  • Proficiency with EDA tools including Innovus, Tempus, and Quantus.
  • Understanding of physical design flows and methodologies, with the ability to meet tight schedules.
  • Ability to work completely on-site in San Jose, California and travel to an Arrow client office when requested.

Nice to have

  • Low-power design and System-on-Chip implementation experience.
  • Expertise in sub-7nm technology nodes.
  • Strong TCL scripting skills for custom Cadence and Synopsys flows.
  • Familiarity with industry-standard EDA tools and capabilities.

Culture & Benefits

  • Medical, dental, and vision insurance.
  • 401(k) with matching contributions.
  • Short-term and long-term disability insurance.
  • Health Savings Account and Health Reimbursement Account options.
  • Paid sick leave, holidays, vacation, tuition reimbursement, and growth opportunities.

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