Physical Design Engineer (AI/EDA)

Location: Palo Alto, United States; on-site

Company

hirify.global is a frontier AI lab developing self-improving systems for chip design and accelerating the path toward artificial superintelligence.

What you will do

• Architect RTL-to-GDSII physical design flows across blocks, subsystems, and full chips.
• Lead hierarchical planning, including partitioning, pin and bump planning, timing and power budgets, and signoff abstraction.
• Own timing, power, physical, EM/IR, DRC, and LVS closure for complex PPA-critical blocks at 5nm/3nm-class nodes through tapeout.
• Deploy AI-driven optimization, ML-based PPA improvement, and LLM agents for orchestration, log triage, constraint validation, and ECO generation.
• Define signoff-quality evaluation criteria for self-improving design models and agents.
• Build reproducible Python and Tcl automation, regression tooling, and QoR-tracking dashboards while partnering with architecture, RTL, DFT, and foundry teams.

Requirements

• 10+ years of hands-on physical design experience spanning synthesis, floorplanning, PDN, placement, CTS, routing, STA, extraction, power/EM/IR analysis, physical verification, LEC, and ECO.
• Experience architecting both top-down and bottom-up hierarchical flows and taking complex blocks, subsystems, or full chips through complete signoff and production tapeout.
• Production fluency with at least one commercial EDA implementation and signoff stack.
• Strong Python and Tcl scripting skills.
• Demonstrated, quantified PPA improvements from AI/ML tooling or LLM-based flow automation.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

Nice to have

• Master’s or PhD focused on VLSI, physical design, or EDA/CAD algorithms.
• Experience with HPC silicon, ML accelerators, CPUs, GPUs, large SoCs, UPF, and 2.5D/3D integration.
• Experience with reinforcement learning, learning-based placement, AI copilots or agents, and AI-for-EDA research.
• Publications at DAC, ICCAD, ISPD, DATE, or similar conferences.