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7 Π΄Π½Π΅ΠΉ Π½Π°Π·Π°Π΄

Package Failure Analysis Engineer

85Β 200 - 139Β 810$
Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
onsite
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
junior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify RU Global, списка ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ с восточно-СвропСйскими корнями
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

ВСкст:
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TL;DR

Package Failure Analysis Engineer (Semiconductor): Supporting root cause determination of assembled package yield loss and in-line failures with an accent on electrical fault isolation and defect characterization. Focus on conducting hands-on lab work, developing innovative failure analysis techniques, and collaborating across organizational boundaries to improve manufacturing yield.

Location: On-site in Phoenix, Arizona. US Citizenship is required due to the necessity of obtaining and maintaining a US Government TS/SCI Security Clearance with Polygraph.

Salary: $85,200–$139,810 USD

Company

hirify.global Foundry is a global leader in semiconductor manufacturing, providing cutting-edge silicon process and packaging technology for the AI era.

What you will do

  • Conduct hands-on lab work to perform fault isolation of electrical failures and defect characterization.
  • Define data acquisition strategies and analysis plans to identify root causes of yield loss.
  • Develop innovative failure analysis techniques and best-known methods (BKMs) to accelerate mechanism understanding.
  • Collaborate with shift engineering technicians, module partners, and integration teams to meet program milestones.
  • Provide technical consultation regarding packaging and assembly improvements.
  • Respond to customer requests and events in a fast-paced manufacturing environment.

Requirements

  • Bachelor's Degree or higher in Materials Science, Mechanical, Chemical, or Electrical Engineering, Physics, or Chemistry.
  • US Citizenship is required.
  • Ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph.
  • Hands-on experience with at least one electrical fault isolation or defect characterization technique.
  • Ability to work a Shift 5 schedule (front half of the week, including Sundays).
  • Strong analytical, problem-solving, and communication skills.

Nice to have

  • Active US Government TS/SCI Security Clearance with Polygraph.
  • Experience with optical analysis techniques (SEM, TEM, x-ray, optical microscopy).
  • Knowledge of electrical circuits and probing equipment (TDR, EOTPR, EBAC, etc.).
  • Familiarity with chemical compositional analysis (EDX, AFM, FTIR, XRD).
  • Experience with CAD software and statistical tools like JMP.

Culture & Benefits

  • Competitive total compensation package including stock bonuses.
  • Comprehensive health, retirement, and vacation benefit programs.
  • Collaborative and inclusive work environment focused on innovation.
  • Opportunities to work with state-of-the-art semiconductor manufacturing technology.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’