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Package Failure Analysis Engineer

85 200 - 139 810$
Формат работы
onsite
Тип работы
fulltime
Грейд
junior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Package Failure Analysis Engineer (Semiconductor Packaging): Determining root causes of package yield loss and in-line failures through hands-on laboratory analysis, electrical fault isolation, and defect characterization with an accent on assembly technologies and manufacturing process improvement. Focus on developing failure analysis techniques, defining data acquisition and analysis plans, and identifying mechanisms that drive corrective actions.

Location: On-site in Phoenix, Arizona, United States. Shift 5 schedule required: days on the front half of the week, AM–PM Sunday through Tuesday and alternating Wednesday days.

Annual salary: $85,200–$139,810 USD.

Company

hirify.global Foundry develops semiconductor process, packaging, manufacturing, supply chain, and final test and assembly technologies for customer products.

What you will do

  • Determine root causes of assembled package yield loss and in-line failures.
  • Design, test, check out, modify, and characterize assembly technologies.
  • Conduct hands-on laboratory analyses and engineering tests to isolate electrical faults and characterize defects and processes.
  • Define data acquisition strategies and analysis plans, then recommend corrective actions to internal customers.
  • Develop innovative failure analysis techniques, best-known methods, and approaches to accelerate failure identification.
  • Collaborate with shift technicians, engineers, module partners, yield and integration teams, program customers, and other internal organizations.

Requirements

  • Bachelor’s degree or higher in Materials Science and Engineering, Mechanical Engineering, Chemical Engineering, Electrical Engineering, Chemistry, Physics, or a related field.
  • US citizenship is required.
  • Ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph.
  • Hands-on experience with at least one electrical fault isolation or defect characterization technique.
  • Strong analytical, problem-solving, communication, presentation, and collaboration skills.
  • Ability to work flexibly with changing priorities, ambiguous responsibilities, and the required shift schedule.

Nice to have

  • Active US Government TS/SCI Security Clearance with Polygraph.
  • Laboratory experience or academic experience with laboratory equipment.
  • Experience with SEM, TEM, X-ray, optical microscopy, electrical circuits, multimeters, TDR, EOTPR, EBAC, RIDR, or ELITE.
  • Experience with EDX, AFM, FTIR, Raman, XRD, or EBSD analysis techniques.
  • Familiarity with CAD software and statistical analysis tools such as JMP.

Culture & Benefits

  • Collaborative environment spanning engineering, manufacturing, yield, integration, and program teams.
  • Opportunities to contribute to semiconductor manufacturing and advanced packaging improvements.
  • Competitive compensation with stock bonuses.
  • Health, retirement, and vacation benefits.

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