Principal Engineer, Physical Design (Semiconductors)

Location: Hsinchu City, Taiwan

Company

hirify.global develops semiconductor solutions and custom Processor/ASIC products for data infrastructure, cloud and AI, carrier, automotive, networking, and 5G/6G applications.

What you will do

• Architect and lead next-generation physical design methodologies and automation flows.
• Provide technical leadership for RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, clock tree synthesis, and timing closure.
• Advise multiple projects, influence design decisions, and resolve complex implementation challenges.
• Collaborate with RTL, verification, CAD, and global cross-functional teams.
• Evaluate EDA tools and technologies with internal CAD teams and external vendors.
• Mentor engineers and represent physical design in technical strategy and roadmap discussions.

Requirements

• Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of progressive experience in back-end physical design and verification, including leadership experience.
• Deep knowledge of RTL-to-GDSII flows, synthesis, place and route, clock tree synthesis, and timing closure.
• Expertise in static timing analysis and power or signal integrity tools, including PrimeTime, Tempus, Voltus, or RedHawk.
• Proficiency in Python, Perl, Tcl, and Makefile for automation and flow development.
• Experience developing and deploying physical design methodologies and flows, with strong communication and mentoring skills.

Nice to have

• Experience working with EDA vendors and evaluating new tools and technologies.

Culture & Benefits

• Collaborative, transparent, and inclusive work environment.
• Competitive compensation and benefits.
• Resources and support for professional growth and development.