pythonperlphysical designvlsipower integritytclclock tree synthesisplace and routeinnovus
Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Текст:
Hirify AI/Оригинал
TL;DR
Principal Engineer - Physical Design (VLSI): Implementing physical design for 32-bit general-purpose and wireless microcontrollers and microprocessors with an accent on floorplanning, timing closure, power integrity, and physical verification. Focus on multi-voltage designs, clock-tree synthesis, place-and-route methodology, flow automation, and delivering designs exceeding multi-million gates.
Location: Nantes, France; travel time 0%–25%
Company
hirify.global is a global technology organization developing products and solutions that power electronic systems.
What you will do
Implement physical design for 32-bit general-purpose and wireless microcontrollers and microprocessors, including floorplanning, placement optimization, clock tree synthesis, routing, crosstalk avoidance, and physical verification.
Perform chip power integrity analysis across multiple voltage domains, including IR drop, signal EM, and Power EM analysis.
Develop hierarchical systems-level designs exceeding multi-million gates, including multi-voltage island-based floorplans and power networks.
Support timing closure, clock tree setup and debugging, place-and-route methodologies, low-power methodologies, and process-node capability optimization.
Develop and automate implementation flows, deliver Physical Verification-clean designs, estimate die size, and approve bond-out designs.
Collaborate with international design and implementation teams, external vendors, and IP sources; take ownership and provide technical leadership.
Requirements
10+ years of applicable technical experience in the physical and timing-related aspects of IC design.
Advanced knowledge of VLSI logic principles and power integrity and reliability analysis, including EM and IR analysis.
Advanced knowledge of place-and-route and low-power methodologies.
Knowledge of clock tree synthesis and debugging and design timing closure.
Experience with 40nm technologies and beyond.
Detailed systems-level floorplanning, power network planning, and multi-voltage or low-power implementation techniques.
Detailed knowledge of Innovus or ICC/ICC2 and Redhawk toolsets.
Proficiency in Tcl, Python, and Perl scripting.
Excellent debugging and analytical skills, good verbal and written communication skills, and strong interpersonal skills.
Self-motivated team-player abilities and collaboration across geographically diverse teams.
Culture & Benefits
Full-time employment within a 17,000-member global organization.
Leadership Passage Programs and opportunities for career growth, autonomy, and leadership.
Values-based decision-making and a focus on innovation and stability.
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