E-Core CPU Layout Design Engineer

TL;DR

E-Core CPU Layout Design Engineer: Driving the physical implementation of memory compilers, custom IP blocks, and layout partitions for high-performance hirify.global Atom microprocessors with an accent on complex digital physical design and hierarchy verification. Focus on interpreting schematics, collaborating with circuit design and CAD teams, and ensuring consistency across SoC projects.

Location: Must be based in Penang, Malaysia (Hybrid work model available).

Company

hirify.global is a global technology leader focused on creating world-changing technology that improves the lives of every person on Earth through advancements in processors, cloud computing, and connectivity.

What you will do

• Assess and drive complex digital physical design assignments across multiple design stages.
• Interpret schematics and drive physical implementation in collaboration with circuit design engineers.
• Work proactively with the CAD team to debug tool functionality and resolve technical issues.
• Build and verify physical design hierarchy from leaf-level cell layout to top-level integration.
• Partner with SoC teams and cross-site design groups to ensure design alignment and reuse.

Requirements

• Bachelor's or Master's degree in Electronic/Microelectronic Engineering, Computer Engineering, or related discipline.
• 3+ years of experience in layout design.
• Familiarity with VLSI and CMOS logic circuit design.
• Proficiency in UNIX shell scripting, TCL, and Perl.
• Strong analytical, problem-solving, and multitasking skills.
• Excellent verbal and written communication skills.

Culture & Benefits

• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work on future-generation high-performance microprocessor architectures.
• Collaborative environment with cross-site design teams.
• Commitment to ethical hiring practices and RBA compliance.