Senior SOC Timing Engineer

Формат работы

onsite

Тип работы

fulltime

Грейд

senior

Английский

Страна

Malaysia

Вакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:

TL;DR

Senior SOC Timing Engineer (FPGA/SoC): Driving timing closure and signoff for FPGA, SoC, and subsystem designs with an accent on static timing analysis, interface timing constraints, and timing convergence. Focus on analyzing physical design and PNR flows, solving timing closure challenges at 10nm or below, and coordinating with design, architecture, and physical design teams.

Location: Penang, Malaysia

Company

hirify.global is the hiring company for this semiconductor timing engineering position.

What you will do

Drive timing closure and final signoff for FPGA, SoC, and subsystem designs.
Perform static timing analysis and derive interface timing constraints for design partitions.
Analyze timing convergence with design and architecture teams.
Collaborate with the physical design team on timing closure.

Requirements

10+ years of experience in timing closure and signoff.
Experience with timing signoff at 10nm or lower technology nodes.
Proficiency with industry-standard physical design EDA tools, including PrimeTime/PTPX.
Good knowledge of physical design and PNR flows.
BE, MS, or PhD in Electronics or Electrical Engineering.
Strong communication, problem-solving, and analytical skills.

Culture & Benefits

Regular full-time employment.
Shift 1 schedule aligned with Malaysia.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →