Staff Digital IC Design Engineer

Location: Ottawa, Canada

Salary: CAD 98,100–130,800 per annum

Company

hirify.global develops semiconductor solutions for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Develop high-speed datapath and control-plane RTL blocks for optical Ethernet transceiver ASICs using Verilog.
• Participate in RTL development, synthesis, static timing analysis, formal equivalence, RTL lint, CDC analysis, and functional verification.
• Integrate and support vendor IP while coordinating with synthesis, back-end, and timing-closure teams.
• Define ASIC specifications and micro-architectures for signal-processing and communications algorithms.
• Perform post-silicon debug and correlation in support of customer deployment.
• Contribute to automation of CAD and EDA flows.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 5+ years of relevant experience, or a master’s degree/PhD with 3+ years of experience.
• 5+ years of experience designing multi-million-gate digital or mixed-signal ICs using 16 nm or smaller technologies.
• Experience across the ASIC design cycle, from micro-architecture and Verilog coding through synthesis, timing closure, post-silicon debug, and lab support.
• Experience with Verilog, SystemVerilog, Python, and Unix Shell.
• Experience with block- and subsystem-level RTL development, as well as gate-level verification and debugging.
• Strong communication, presentation, multitasking, adaptability, and teamwork skills.

Culture & Benefits

• Collaborative, transparent, and inclusive work environment.
• Competitive compensation and benefits.
• Resources and support for professional growth and development.
• Interview use of AI tools, including transcription, answer-generation, and automated note-taking tools, is prohibited.
• Access to export-controlled technology may require eligibility under U.S. export control regulations and an export license review.