Design Engineer I (DFT)

Location: Cary, United States of America

Annual salary: $88,900–$165,100 for California; incentive compensation, equity, and benefits may also apply.

Company

hirify.global develops technology for designing and validating complex chips, including the Palladium platform.

What you will do

• Define and implement SoC-level DFT architectures for large and complex designs.
• Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN, and iJTAG.
• Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
• Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
• Support post-silicon debug, failure analysis, and yield learning.
• Collaborate with RTL, verification, physical design, and operations teams.

Requirements

• Bachelor's degree.
• At least 3 years of hands-on experience in SoC DFT.
• Strong expertise in SCAN, ATPG, and MBIST.
• Experience with pre-silicon validation and post-silicon debugging.
• Strong problem-solving skills and the ability to work in a cross-functional engineering environment.

Nice to have

• Scripting experience with TCL, Perl, Python, or equivalent for flow automation and analysis.
• Experience with IP-level DFT integration and reuse.
• Exposure to low-power DFT and complex clocking architectures.
• Familiarity with manufacturing test flows and silicon yield improvement.

Culture & Benefits

• Paid vacation and paid holidays.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Medical, dental, and vision plan options.
• Potential bonus, equity, and other incentive compensation.