Principal NPI Product Engineer (Semiconductor)

Location: Hybrid, 4 days in office Monday–Thursday in Burlington or Ottawa, Canada, or Bristol, UK; the posting also lists San Diego, CA, USA.

Salary: CAD 110,000–140,000 per year.

Company

hirify.global develops high-performance optical and analog/mixed-signal ICs using CMOS and BiCMOS technologies for optical networking infrastructure.

What you will do

• Own NPI programs from product concept and silicon bring-up through product release and full-volume manufacturing transfer.
• Coordinate Design, Marketing, Validation, Test, Characterization, Quality, Reliability, Applications Engineering, and Operations teams.
• Define and drive Design for Testability and Design for Manufacturability requirements.
• Lead ATE test development, product characterization, ATE-to-bench correlation, and production test limit setting.
• Analyze PVT data, model yield, plan DOE activities, reduce test time, and optimize production yield.
• Lead failure analysis, root-cause investigations, CAPA closure, reliability qualification, and continuous improvement initiatives.

Requirements

• Bachelor’s degree in Electrical Engineering or a related field; a master’s degree is strongly preferred.
• 10+ years of experience in semiconductor product engineering, test engineering, or design engineering.
• Hands-on experience with silicon bring-up, characterization, production transfer, ATE test development, ATE-to-bench correlation, and production test limit setting.
• Strong knowledge of DfT and DfM principles and proficiency with statistical analysis tools such as JMP or Excel.
• Scripting or automation experience with Python, TCL, or an equivalent language.
• Strong analytical, problem-solving, and cross-functional communication skills.

Nice to have

• Experience with analog/mixed-signal or optical ICs, including TIA, CDR, LimitAmp, or high-speed SerDes.
• Familiarity with Advantest or Teradyne ATE platforms.
• Experience with JEDEC reliability qualifications such as HTOL, HAST, ESD, and latch-up.
• Exposure to ATPG, MBIST, boundary scan, foundry, or OSAT processes.

Culture & Benefits

• Work on CMOS and BiCMOS ICs supporting 400G, 800G, and 1.6T optical networking infrastructure.
• Full program ownership from the first day, with direct collaboration across design, reliability, and fab functions.
• Global collaboration across sites in Canada, the UK, Mexico, the USA, and Asia.
• Competitive compensation, benefits, and professional development opportunities.