Senior DFT Design Engineer

Location: San Jose, California, United States; onsite role. Applicants must be eligible for required U.S. export authorizations.

Salary: $187,000–$270,700 USD annually for the Bay Area California location, plus incentive opportunities.

Company

hirify.global develops advanced semiconductor and IC technologies, including FPGA, processor, DSP, SERDES, IO, and multi-die solutions.

What you will do

• Define and implement DFT architectures and specifications for FPGA, processor, DSP, SERDES, IO, and 2.5D/3D multi-die designs.
• Insert test logic, generate ATPG patterns, and perform pre-silicon validation for manufacturability and quality.
• Collaborate with IP and integration design teams to align DFT features with circuit functionality and timing.
• Partner with test development teams on silicon bring-up, debug, and production readiness.
• Develop DFT methodologies and automation flows to improve scalability and validation efficiency.
• Optimize test coverage, test cost, yield, and debug support.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 10+ years of relevant industry experience, or a master’s degree with 8+ years.
• 8+ years of DFT design and verification experience at RTL and gate level.
• Experience with synthesis, scan insertion, ATPG, simulation, debug, and STA tools.
• Design automation experience and scripting proficiency in Perl or TCL.
• Eligibility for any required U.S. export authorizations.

Nice to have

• Experience with test compression, MBIST/LBIST, and advanced fault models.
• Experience with 2.5D/3D multi-die designs and high-speed IO/SerDes DFT.

Culture & Benefits

• Opportunity to work with IP, integration design, and test development teams.
• Work on advanced semiconductor technologies and complex circuit designs.
• Incentive opportunities based on individual and company performance.