DFT Engineer (AI)

Location: On-site in Palo Alto, California, United States

Company

hirify.global is a frontier AI lab building self-improving systems for chip design and accelerating the development of advanced silicon.

What you will do

• Own DFT architecture and insertion for complex advanced-node chips, including hierarchical scan, compression, BIST, MBIST, BISR, boundary scan, and IJTAG.
• Define fault models and coverage strategies, generate and verify ATPG patterns, and drive DFT signoff through tapeout.
• Lead post-silicon testing from first silicon to production, including ATE bring-up, CP, FT, SLT, scan diagnosis, failure analysis, and yield improvement.
• Integrate DFT with RTL, design verification, synthesis, physical design, timing, and gate-level simulation flows.
• Develop AI-native DFT methods and reusable automation, checks, and evaluation targets.
• Collaborate with foundry and OSAT partners and contribute directly to RTL and DV work when needed.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 5+ years of hands-on DFT experience across the full lifecycle of complex SoCs or IPs.
• Production experience with a DFT stack, gate-level simulation, Tcl and Python scripting, and sufficient Verilog/SystemVerilog for test logic and testbench development.
• Experience taking silicon from tapeout to production, including ATPG and MBIST pattern bring-up on ATE and debugging CP, FT, and SLT failures.
• Experience working directly with foundry and OSAT partners.
• Demonstrated use of AI coding or agentic tools in engineering work and an understanding of their application in DFT.

Nice to have

• Master's or PhD in EE, CE, CS, or a related field focused on VLSI test, fault tolerance, reliability, or EDA/CAD algorithms.
• DFT experience with high-performance computing silicon, advanced packaging, ML accelerators, CPUs, GPUs, or large SoCs.
• Experience with test program development, characterization, HVS, HTOL, yield analytics, wafer-map correlation, outlier screening, RMA, and failure analysis.
• Quantified AI/ML improvements in chip design or test flows, or experience building AI-assisted design and verification systems.
• Publications or open-source contributions in DFT, testing, or AI for chip design.

Culture & Benefits

• Work in a small, fast-paced team defining foundational DFT methodology and infrastructure from the ground up.
• Collaborate with experienced chip designers, researchers, and engineers from leading technology companies and academic institutions.
• Contribute directly to AI systems that improve chip design, testing, coverage, test time, and DPPM.