Design Verification Lead (AI)

Location: Hybrid, requiring 3 days per week onsite at the HQs in Vancouver, WA, or Chandler, AZ. Remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.

Salary: $160,000–$190,000 annual base salary for Member of Technical Staff.

Company

hirify.global is a well-funded semiconductor startup developing chiplet power delivery technology for high-performance processors, AI, and advanced computing.

What you will do

• Lead verification planning and execution for complex digital and mixed-signal SoC/IP subsystems from RTL through gate-level simulation.
• Architect and maintain scalable SystemVerilog- and UVM-based verification environments, reusable verification components, RAL models, and protocol infrastructure.
• Develop directed, constrained-random, regression, corner-case, CDC, assertion, formal verification, and functional coverage strategies.
• Build and optimize simulation and regression flows using Xcelium and VCS, including SDF-annotated gate-level simulation.
• Debug RTL, testbench, simulation, timing, reset, initialization, connectivity, and gate-level failures using waveform and log analysis.
• Provide technical leadership, mentor verification engineers, and collaborate with RTL, analog, architecture, and silicon validation teams.

Requirements

• Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
• 10+ years of digital SoC verification experience with ownership of subsystems or full-chip verification.
• Strong expertise in Verilog, SystemVerilog, UVM, class-based verification, constrained-random and coverage-driven verification, and regression automation.
• Experience with SVA, formal verification, CDC/RDC, mixed-signal subsystems, SoC integration, and protocols including AMBA, I²C, I3C, SPI, JTAG, and OBI.
• Programming and automation experience with Python, Perl, and UNIX/Linux shell scripting, plus hands-on testbench, driver, monitor, scoreboard, assertion, and reusable verification IP development.
• Experience with industry-standard EDA tools from Synopsys and Cadence, along with strong debugging, communication, leadership, and mentoring skills.

Nice to have

• Working knowledge of PMIC architectures and power management principles.
• Additional experience with formal verification techniques.

Culture & Benefits

• Stock option grant.
• Comprehensive health, dental, and vision benefits.
• 401(k) plan.
• Collaborative work with RTL, analog, architecture, and silicon validation teams.