4 дня назад
Senior ASIC Design Engineer
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior ASIC Design Engineer (Verilog/SystemVerilog, AI and HPC Networking): Developing RTL for high-speed data paths, packet processing, and Host Fabric Interface subsystems in ASICs for AI and high-performance computing networks with an accent on Ethernet, timing closure, and power-aware design. Focus on collaborating across verification, physical design, hardware, firmware, and software teams to debug system-level issues and validate post-silicon performance.
Location: Remote within the United States; the role is associated with Austin, Texas.
Company
develops high-performance scale-out networking solutions that integrate hardware, software, and system technologies for AI and high-performance computing data centers.
What you will do
- Implement RTL designs in Verilog and SystemVerilog for high-speed data paths and packet-processing logic.
- Collaborate with verification engineers on block-level and system-level test plans and design coverage.
- Define timing constraints and work with Physical Design engineers on timing closure.
- Support post-silicon validation and debug ASIC issues with hardware, firmware, and software teams.
- Optimize performance and develop power-aware strategies for Host Fabric Interface subsystems.
Requirements
- B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field.
- 8+ years of post-college digital design experience with Verilog and SystemVerilog.
- Experience designing RTL for high-speed data paths or packet processing in ASICs.
- Deep understanding of Host Ethernet Adapter architectures, timing closure, and modern physical design methodologies.
- Proven ability to perform system-level debugging and root cause analysis.
- Must reside within the United States; strong verbal and written communication skills are required.
Nice to have
- Knowledge of Ethernet architecture and networking protocols, including TCP/IP, RDMA/RoCE, or IPSec.
- Experience with RTL development for Ethernet host adapters and system debugging.
- Expertise in multiple clock-domain designs and asynchronous interfaces.
- 5+ years of experience with TCL, Python, or Perl scripting.
- Familiarity with Design Compiler, Spyglass, or PrimeTime.
Culture & Benefits
- Flexible remote, hybrid, and onsite work environment across a global organization.
- Opportunities to work on AI, HPC, semiconductor, and high-performance networking technologies.
- Compensation package including equity, cash, and performance-based incentives.
- Medical, dental, vision, disability, life, dependent care, accidental injury, and pet insurance.
- Paid holidays, sick time, bonding leave, pregnancy disability leave, 401(k) with company match, and Open Time Off for eligible full-time exempt employees.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →
Похожие вакансии
Tenstorrent
10 дней назад
Midcore Design Verification Engineer (RISC-V)
10 дней назад
SoC Micro-Architect & RTL Designer (AI)
200 000$
Tenstorrent
4 дня назад
Physical Design Engineer (AI)
10 дней назад
Principal Physical Design Engineer (AI)
300 000 - 400 000$
11 дней назад
Senior Design Verification Engineer (Digital)
130 000 - 200 000$
Tenstorrent
4 дня назад
Sr. Staff Engineer, RTL Physical Implementation Lead (AI)
100 000 - 500 000$