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4 дня назад

Senior ASIC Design Engineer

Формат работы
remote (только USA)
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior ASIC Design Engineer (Verilog/SystemVerilog, AI and HPC Networking): Developing RTL for high-speed data paths, packet processing, and Host Fabric Interface subsystems in ASICs for AI and high-performance computing networks with an accent on Ethernet, timing closure, and power-aware design. Focus on collaborating across verification, physical design, hardware, firmware, and software teams to debug system-level issues and validate post-silicon performance.

Location: Remote within the United States; the role is associated with Austin, Texas.

Company

hirify.global develops high-performance scale-out networking solutions that integrate hardware, software, and system technologies for AI and high-performance computing data centers.

What you will do

  • Implement RTL designs in Verilog and SystemVerilog for high-speed data paths and packet-processing logic.
  • Collaborate with verification engineers on block-level and system-level test plans and design coverage.
  • Define timing constraints and work with Physical Design engineers on timing closure.
  • Support post-silicon validation and debug ASIC issues with hardware, firmware, and software teams.
  • Optimize performance and develop power-aware strategies for Host Fabric Interface subsystems.

Requirements

  • B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field.
  • 8+ years of post-college digital design experience with Verilog and SystemVerilog.
  • Experience designing RTL for high-speed data paths or packet processing in ASICs.
  • Deep understanding of Host Ethernet Adapter architectures, timing closure, and modern physical design methodologies.
  • Proven ability to perform system-level debugging and root cause analysis.
  • Must reside within the United States; strong verbal and written communication skills are required.

Nice to have

  • Knowledge of Ethernet architecture and networking protocols, including TCP/IP, RDMA/RoCE, or IPSec.
  • Experience with RTL development for Ethernet host adapters and system debugging.
  • Expertise in multiple clock-domain designs and asynchronous interfaces.
  • 5+ years of experience with TCL, Python, or Perl scripting.
  • Familiarity with Design Compiler, Spyglass, or PrimeTime.

Culture & Benefits

  • Flexible remote, hybrid, and onsite work environment across a global organization.
  • Opportunities to work on AI, HPC, semiconductor, and high-performance networking technologies.
  • Compensation package including equity, cash, and performance-based incentives.
  • Medical, dental, vision, disability, life, dependent care, accidental injury, and pet insurance.
  • Paid holidays, sick time, bonding leave, pregnancy disability leave, 401(k) with company match, and Open Time Off for eligible full-time exempt employees.

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