9 дней назад
Senior Technical Staff Engineer (SOC Verification)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Technical Staff Engineer (SOC Verification) (SystemVerilog/UVM): Architecting and executing SoC-level verification for next-generation ARM-based and proprietary microcontrollers with an accent on functional safety, coverage closure, and first-pass silicon success. Focus on developing reusable verification environments, debugging full-chip issues, driving automation and AI-assisted workflows, and mentoring engineers across verification programs.
Location: Chandler, Arizona, United States
Company
develops microcontroller products and semiconductor technologies for global markets.
What you will do
- Own comprehensive SoC-level verification plans from architectural specification through tape-out.
- Develop SystemVerilog and UVM verification environments, reusable testbench components, stimulus, checkers, assertions, and coverage models.
- Verify digital IP, subsystem integrations, and full-chip designs across RTL, gate-level, and simulation environments.
- Develop functional safety strategies, fault-injection tests, safety metrics, and coverage goals.
- Debug issues across architecture, RTL design, firmware interaction, and verification infrastructure.
- Drive verification methodology, automation, formal verification, AI-assisted workflows, and technical mentoring across projects.
Requirements
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
- 12+ years of experience in digital design verification, including successful SoC or MCU tape-outs.
- Strong expertise in SystemVerilog, UVM, and coverage-driven verification methodologies.
- Hands-on experience verifying complex SoCs with ARM or comparable embedded processor architectures.
- Deep understanding of AMBA protocols, including AXI, AHB, and APB, plus strong debugging and technical communication skills.
- Ability to collaborate across geographically distributed engineering teams and influence technical decisions.
Nice to have
- Experience with formal verification tools such as JasperGold or VC Formal.
- Expertise in gate-level, low-power, and power-aware verification.
- Knowledge of functional safety standards and approaches, including ISO 26262 and fault-injection analysis.
- Verification automation and scripting experience with Python, Perl, or similar tools, including AI-assisted technologies.
- Experience with post-silicon validation, mixed-signal verification, or technical mentoring.
Culture & Benefits
- Full-time employment within a 17,000-member global organization.
- Technical individual-contributor role with broad influence on architecture, methodology, automation, and product quality.
- Career development through leadership and employee development programs.
- Travel expectation of 0%–25%.
- Work involves collaboration with global engineering teams and primarily seated activity.
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