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6 дней назад

Principal Engineer, Mixed Signal Logic Design Engineer

220 920 - 311 890$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

Текст:
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TL;DR

Principal Engineer, Mixed Signal Logic Design Engineer (Mixed Signal): Developing logic design, RTL coding, and simulation for mixed signal and high-speed IPs with an accent on power, performance, area, and timing optimization. Focus on designing IP blocks and subsystems for full chip integration and mentoring technical leaders to drive technical direction across the organization.

Location: On-site presence required in Folsom or San Jose, California, US

Salary: $220,920.00 - 311,890.00 USD

Company

hirify.global is a global leader in semiconductor innovation, focusing on scalable engineering solutions across product enablement, custom ASIC, and foundry services.

What you will do

  • Develop logic design, RTL coding, and simulation for mixed signal and high-speed IPs to generate cell libraries and functional units.
  • Define architecture and microarchitecture features for IP blocks and subsystems.
  • Optimize logic to meet strict power, performance, area, and timing goals.
  • Review verification plans and implement corrective measures for failing RTL tests to ensure feature correctness.
  • Support SoC customers to ensure high-quality integration of the IP block.
  • Act as a domain expert to influence technical direction and mentor other technical leaders.

Requirements

  • Bachelor's degree in Computer Science, Electrical Engineering, or a related STEM field with 12+ years of experience (or Master's with 10+ / PhD with 8+).
  • Proficiency in System Verilog, including experience with OVM/UVM methodologies.
  • Demonstrated experience in developing IP or SoC verification environments and executing validation plans.
  • Must be able to work on-site in Folsom or San Jose, California.

Nice to have

  • 3+ years of experience with DFI/DDR/LPDDR Protocols.
  • Experience in DDR Phy or Memory Controller verification.
  • Strong problem-solving skills and a proactive approach to complex technical challenges.

Culture & Benefits

  • Competitive total compensation package including pay and stock bonuses.
  • Comprehensive benefit programs covering health, retirement, and vacation.
  • Opportunity to work in a dynamic, forward-thinking team redefining the future of innovation.

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