RTL2GDS, Product Engineering Architect (ASIC)

Location: San Jose, California, United States

Annual salary: $178,500–$331,500, plus potential bonus, equity, and benefits.

Company

hirify.global develops digital and signoff software tools for advanced chip design.

What you will do

• Support hirify.global digital products as a technical resource in place-and-route and RTL-to-GDSII methodologies.
• Collaborate with R&D, application engineering, product marketing, and release teams.
• Track and resolve customer issues and provide organized technical solutions.
• Conduct design benchmarks and analyze implementation results.
• Develop innovative flows and methodologies tailored to customer needs.

Requirements

• Bachelor’s degree in Electrical Engineering and at least seven years of digital implementation experience as a design or product engineer.
• Strong understanding of ASIC design methodologies across the RTL-to-GDSII flow.
• Hands-on experience with timing closure and PPA optimization at 7nm and below.
• Knowledge of VLSI physical design, timing analysis, clock tree synthesis, routing optimization, and silicon signoff challenges.
• Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 7nm and below.
• Strong verbal and written communication skills.

Nice to have

• Proficiency in scripting languages or AI tools for productivity enhancement.

Culture & Benefits

• Paid vacation and paid holidays.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Medical, dental, and vision plan options.
• Potential bonus and equity compensation.