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3 дня назад

Senior Digital Mixed-Signal (DMS) Verification Engineer (ASIC)

108 000 - 172 800$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
c1
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior Digital Mixed-Signal (DMS) Verification Engineer (ASIC): Developing and maintaining advanced UVM-based testbenches for complex mixed-signal ASIC products with an accent on verification quality and automation. Focus on integrating SystemVerilog Assertions (SVA), exploring AI-assisted verification workflows, and bridging US and Asia design centers.

Location: Based in Mendota Heights, MN or Broomfield, CO (USA)

Salary: $108,000 - $172,800

Company

A global technology leader and Fortune 500 company specializing in semiconductor innovation and AI infrastructure.

What you will do

  • Architect and maintain advanced UVM-based testbenches for the functional verification of complex mixed-signal ASIC products.
  • Integrate new methodologies, including SystemVerilog Assertions (SVA) and UVM/OVM, to reduce validation bottlenecks.
  • Act as the primary technical liaison between local US digital design teams and worldwide verification teams.
  • Lead initiatives to integrate modern automation and AI-assisted verification workflows to accelerate debug efficiency.
  • Own verification efforts at block and system levels to drive functional and code coverage to closure for major tape-out projects.

Requirements

  • 5+ years of hands-on experience in digital verification of mixed-signal ASICs or SoCs.
  • Deep expertise in coverage-driven verification processes and UVM/OVM frameworks.
  • Strong understanding of event-driven simulator-based modeling and analog/digital boundary interactions.
  • Bachelor's in EE, CE, or CS with 8+ years of experience, or Master's in Engineering with 6+ years of experience.
  • Excellent English communication skills.
  • Must be based in Mendota Heights, MN or Broomfield, CO.

Nice to have

  • Experience with Mixed-signal ASIC UVM / OVM.
  • Hands-on experience with SystemVerilog Assertions (SVA) and behavioral modeling of analog circuits.
  • Proficiency in scripting for automation of verification workflows and regression management.

Culture & Benefits

  • Competitive annual base salary, discretionary bonuses, and RSU packages.
  • Comprehensive medical, dental, and vision insurance plans.
  • 401(K) participation with company matching and Employee Stock Purchase Program (ESPP).
  • Company paid holidays, paid sick leave, and vacation time.
  • Career stability within a Fortune 500 semiconductor leader in high-quality-of-life locations.

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