Physical Design Engineer (AI)

TL;DR

Physical Design Engineer (AI): Developing best-in-class silicon for high-performance and sustainable Generative AI with an accent on scalable physical design methodology from RTL to GDS. Focus on owning entire subsystems, driving sign-off reviews, and optimizing PPA metrics.

Location: Hybrid role based in the San Francisco Bay Area

Salary: $200,000 - $300,000 + equity + benefits

Company

A company founded by industry veterans pushing the boundaries of LLMs through cutting-edge semiconductor and AI products.

What you will do

• Contribute to silicon and physical design methodology across blocks, subsystems, and full-chip designs from RTL to GDS.
• Own entire subsystems and drive intermediate and sign-off reviews.
• Monitor and report execution progress based on key PPA metrics.
• Collaborate closely with design, verification, and DFT teams to ensure silicon success.

Requirements

• BSEE/CE or MSEE/CE degree.
• Minimum five years of professional industry experience.
• RTL-to-silicon experience in driving physical design for ASIC/SOC subsystems or top-level functions.
• Production-proven expertise in floorplanning, place and route, clock tree insertion/analysis, timing analysis, physical verification, and electrical sign-off.

Culture & Benefits

• Competitive base salary with equity and comprehensive benefits.
• Opportunity to work within a high-performing team of industry veterans.
• Engagement with cutting-edge technology in the field of Generative AI and LLMs.