IC Design Engineer (ASIC)

TL;DR

IC Design Engineer (ASIC): Implementing new technologies for low-power consumer electronics and high-performance satellite projects with an accent on physical implementation and timing closure. Focus on floorplanning, multi-power domain planning, and physical verification for block and chip-level designs.

Location: San Jose, CA or Irvine, CA, USA

Salary: $127,100 - $203,400

Company

Global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Lead and implement chips for consumer devices and satellite projects using 40nm, 16nm, and 7nm nodes.
• Perform physical implementation of blocks and top-level designs.
• Manage floorplanning, including multi-power domains, PG planning, block-shaping, and clock-tree implementation.
• Conduct physical verification and Static/Dynamic IR drop analysis, including Signal and Power EM checks.
• Develop methodology and flows for physical design and timing closure.
• Collaborate with Synthesis, STA, and RTL design teams on physical implementation and power-intent requirements.

Requirements

• BS in Electrical Engineering with 12+ years of experience or MS with 10+ years.
• Proven track record with multiple tapeouts.
• Extensive hands-on expertise in Cadence Innovus, VCLP, Formality, LEC, and Calibre.
• Proficiency in TCL scripting.

Nice to have

• Knowledge of Python.
• Knowledge of ESD, IO padring, and analog integration.
• Exposure to various packages, including flip-chip and wlcsp.
• Familiarity with AI tools.

Culture & Benefits

• Comprehensive medical, dental, and vision plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Company paid holidays, paid sick leave, and vacation time.
• Employee Assistance Program (EAP).