Mid-level Physical Design Engineer CPU

Location: On-site in Hillsboro, Oregon, United States

Annual salary: $122,440–$232,190 USD

Company

hirify.global develops semiconductor technologies and next-generation CPU platforms for client, server, IoT, and AI applications.

What you will do

• Implement physical design for CPU core blocks and subsystems across the RTL-to-GDS flow.
• Perform synthesis, floor planning, place and route, design closure, static timing analysis, and power analysis.
• Debug timing, power, design rule, electrical, noise, and electromigration violations.
• Contribute to timing, power, and area targets for advanced-process silicon designs.
• Develop and maintain design automation scripts using TCL and other interpreted languages.
• Collaborate with RTL design, verification, clocking, architecture, and full-chip integration teams.

Requirements

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field with 5+ years of relevant experience, or a master’s degree with 3+ years of relevant experience.
• Experience with integrated circuit design tools such as Synopsys or Cadence, including synthesis, place and route, static timing analysis, and design closure.
• Experience with physical verification, including formal equivalence, DRC/LVS, electrical rules, noise, and electromigration checks.
• Scripting experience with TCL and at least one additional language such as Perl, Python, or Ruby.
• Experience synthesizing a digital logic block integrated into a large SoC or IP.
• Ability to work on-site in Hillsboro, Oregon, United States.

Nice to have

• CPU micro-architecture exposure.
• Experience with floor planning, routing, clock distribution, static timing, noise analysis, reliability verification, RTL-to-GDS methodologies, and formal equivalence.
• Experience with Synopsys Fusion Compiler, ICC2, PrimeTime, or Cadence Genus and Innovus.

Culture & Benefits

• Work on CPU core designs for client, server, IoT, and AI platforms.
• Collaborate with experienced engineers across architecture, design, and full-chip integration.
• Access challenging silicon design problems, modern tools, and continuous learning opportunities.
• Benefits include competitive pay, stock bonuses, health coverage, retirement programs, and vacation.
• Work in an inclusive environment that values collaboration and diverse perspectives.