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2 дня назад

Mid-Level Physical Design Engineer CPU (AI)

122 440 - 232 190$
Формат работы
onsite
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Mid-Level Physical Design Engineer CPU (AI): Delivering high-performance, power-efficient silicon for client, server, IoT, and AI platforms with an accent on the RTL-to-GDS flow. Focus on block-level implementation, achieving PPA targets, and solving complex timing and power violations.

Location: On-site in Hillsboro, Oregon, US

Salary: $122,440.00 - $232,190.00 USD

Company

hirify.global is a global leader in semiconductor manufacturing, inventing boundary-pushing technology for processors and connectivity solutions.

What you will do

  • Execute physical design implementation for CPU core blocks or subsystems across the RTL-to-GDS flow.
  • Perform synthesis, floor planning, place and route (PnR), and design closure activities.
  • Conduct static timing analysis (STA), power analysis, and physical verification.
  • Identify and debug timing, power, and design rule violations to meet PPA targets.
  • Develop and maintain automation scripts using TCL and Python.
  • Collaborate with RTL design, verification, clocking, and full-chip integration teams.

Requirements

  • Bachelor's degree in Computer/Electrical Engineering with 5+ years of experience, or a Master's with 3+ years.
  • Experience with integrated circuit design tools (Synopsys or Cadence).
  • Proficiency in logic synthesis, place and route, STA, and design closure.
  • Experience in chip physical design verification (DRC/LVS, Noise, electro-migration).
  • Scripting skills in TCL and at least one other language (Perl, Python, or Ruby).
  • Experience with synthesis of digital logic blocks integrated into large SoCs or IPs.

Nice to have

  • Industry exposure to CPU Micro-Architecture.
  • Advanced knowledge of floor-planning, routing techniques, and clock distribution.
  • Experience with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (Genus/Innovus).

Culture & Benefits

  • Opportunity to work on cutting-edge CPU designs used worldwide in AI and IoT platforms.
  • Competitive total compensation package including stock bonuses.
  • Comprehensive health, retirement, and vacation benefit programs.
  • Collaborative environment that values inclusion and diverse perspectives.
  • Strong emphasis on continuous technical learning and skill development.

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