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Physical Design Engineer (Semiconductors)

Формат работы
onsite
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
Mexico
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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TL;DR
Physical Design Engineer (Semiconductors): Responsible for block-level and subsystem-level EM/IR analysis and closure to deliver high-performance semiconductor solutions with an accent on reliability closure and physical design implementation from RTL to GDS. Focus on optimizing power, frequency, and area using industry-standard EDA tools and refining physical design methodologies.

Location: On-site in Guadalajara, Mexico. Must have unrestricted, permanent right to work in Mexico (not eligible for visa or immigration sponsorship).

Company

hirify.global's Central Engineering Group (CEG) is a data-driven organization building scalable engineering solutions across product enablement, custom ASIC, and foundry enablement.

What you will do

  • Execute physical design implementation from RTL to GDS, including synthesis, place and route, clock tree synthesis, and floor planning.
  • Conduct verification and signoff, including formal equivalence, reliability, static and dynamic power integrity, and timing analysis.
  • Identify and resolve design violations to optimize current and future product architectures.
  • Optimize design metrics such as power, frequency, and area using industry-standard EDA tools.
  • Develop and improve physical design methodologies, automation flows, and processes.
  • Collaborate with cross-functional teams to ensure designs meet quality and performance standards.

Requirements

  • Bachelor's (3+ years), Master's (2+ years), or PhD in Electronics Engineering, Computer Engineering, or a related field.
  • Proficiency in scripting languages (Python, Tcl, Perl) for design flow automation.
  • Expertise in static timing analysis (STA) and layout verification tools such as Calibre DRC.
  • Experience with physical design implementation for custom IP and SoC designs using Synopsys or Cadence.
  • English: Intermediate to advanced level required.
  • Must have unrestricted, permanent right to work in Mexico.

Nice to have

  • Working knowledge of Synopsys/Ansys signoff tools such as PrimeTime PX, PrimeRail, or Redhawk.
  • Understanding of power delivery networks, reliability fundamentals, and signoff criteria.
  • Experience with Physical Design ECO cycles and closure loops.
  • Hands-on experience with EM/IR analysis and closure for advanced nodes (3nm or below).

Culture & Benefits

  • Opportunity to work on world-class semiconductor solutions that shape the future of technology.
  • Role within a high-impact, data-driven organization (CEG).
  • Commitment to ethical hiring practices and Responsible Business Alliance (RBA) compliance.

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