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3 дня назад

Design Verification Engineer (AI Hardware)

150 000 - 275 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Design Verification Engineer (AI Hardware): Developing and validating UVM/SystemVerilog-based verification environments for IP subsystems and interfaces in frontier AI inference hardware with an accent on functional correctness, performance, and protocol compliance. Focus on closing coverage, exposing corner-case bugs, integrating vendor IP, and validating interactions across the full hardware-software stack.

Location: On-site in Austin, with regular time spent working alongside the team in San Jose. During the first quarter, approximately two weeks per month are expected at the San Jose headquarters; afterward, approximately one week per month.

Salary: $150K–$275K plus significant equity.

Company

hirify.global builds frontier AI inference hardware by co-designing chips, racks, software, and manufacturing systems for high throughput and low latency.

What you will do

  • Own end-to-end design verification for IP subsystems such as PCIe, Ethernet, CPU, low-power peripherals, and sensors.
  • Understand vendor IP configurations and coordinate with internal IP teams.
  • Develop and maintain UVM/SystemVerilog verification environments for functional correctness, performance, and specification compliance.
  • Collaborate with integration and SoC design verification teams to validate external IP within the chip architecture.
  • Define coverage metrics, analyze gaps, and drive coverage closure and verification sign-off across corner cases and stress scenarios.

Requirements

  • 5+ years of design verification experience.
  • Hands-on experience with SystemVerilog, UVM, and scalable, reusable testbench development.
  • Experience with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
  • Ability to investigate complex verification challenges and identify corner-case bugs.
  • Experience collaborating across RTL design, software, emulation, integration, and SoC verification teams.
  • Ability to work on-site in Austin and regularly work from the San Jose headquarters.

Nice to have

  • Experience managing vendors and integrating IP or VIP.
  • Additional UVM/SystemVerilog experience.

Culture & Benefits

  • Medical, dental, and vision coverage with generous premium support.
  • $500 monthly credit for waiving medical benefits.
  • Wellness benefits for fitness, mental health, and other needs.
  • Daily lunch and dinner at the office.
  • Unlimited compute budget subject to return-on-investment justification.
  • Engineering and research work across disciplines without strict boundaries.

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