Senior Principal Engineer – Hardware Chip Lead, Connectivity BU (Optical DSP)

Location: Santa Clara, CA, United States

Salary: $182,360–$273,200 per annum

Company

hirify.global develops semiconductor solutions and advanced ASICs that support enterprise, cloud, AI infrastructure, and carrier data networks.

What you will do

• Own the hardware direction and execution of an Optical DSP chip program from plan of record through mass production.
• Finalize product requirements and bring-up requirements with architecture, marketing, and applications engineering.
• Coordinate analog, digital, design verification, DFT, physical design, STA, firmware, validation, ATE/test, product engineering, and quality teams.
• Lead chip design across advanced TSMC 2nm, 3nm, and 5nm CMOS nodes, including architecture, RTL, physical design, timing closure, DFT, and tape-out.
• Drive silicon bring-up, PVT characterization, qualification, production release, and post-silicon debugging across global sites.
• Mentor engineers and improve design methodology, execution flows, and hardware quality.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of professional experience; or a master’s degree with 10–12 years; or a PhD with 8–10 years.
• Proven experience as a chip lead or equivalent technical owner for complex SoC/ASIC programs from architecture through tape-out and post-silicon productization.
• Deep expertise in high-speed mixed-signal SoC design, including 100G+/lane SerDes, DSP datapaths, analog/digital integration, and advanced CMOS processes.
• Strong knowledge of the ASIC flow, including micro-architecture, RTL, synthesis, DFT, physical design, STA, timing closure, and tape-out.
• Experience leading multi-disciplinary teams through silicon bring-up, validation, ATE test development, characterization, HTOL, ESD, LU, and production release.
• Excellent communication and presentation skills, with the ability to represent hardware engineering to business-unit leadership and cross-functional stakeholders.

Nice to have

• Experience with optical DSP, coherent or direct-detect transceiver architectures, or high-speed retimers.
• Familiarity with eAVS or similar power optimization subsystems.
• Knowledge of silicon photonics integration and module-level validation.
• Experience in a multi-site, globally distributed engineering organization.

Culture & Benefits

• Work with a global, multi-site Optical DSP engineering organization spanning the United States, Canada, Italy, Vietnam, and Argentina.
• Employee stock purchase plan with a two-year lookback.
• Family support programs and mental and physical health resources.
• Recognition and service awards.
• Access to advanced semiconductor programs for high-bandwidth data transmission and AI infrastructure.