Senior Principal Engineer (Hardware Chip Lead)

TL;DR

Senior Principal Engineer (Hardware Chip Lead): Leading the design and execution of next-generation Optical DSP ASICs for data centers and AI infrastructure with an accent on high-speed SerDes and advanced CMOS nodes. Focus on full-cycle chip ownership from architecture and RTL to tape-out and silicon validation.

Location: Santa Clara, CA

Salary: $182,360 - $273,200 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Act as the primary hardware technical owner for ODSP chip programs from Plan of Record (POR) through Mass Production (MPR).
• Define high-level technical solutions across the hardware stack, including analog/digital integration and SoC architecture.
• Lead end-to-end chip design execution across advanced CMOS nodes (TSMC 2nm/3nm/5nm), covering RTL, physical design, and timing closure.
• Drive chip bring-up, silicon validation, and post-silicon debug coordinating multi-site global teams.
• Collaborate with cross-functional teams including DV, DFT, firmware, and ATE/test engineering.
• Mentor and develop engineers within the ODSP hardware organization to build technical depth.

Requirements

• Bachelor's degree in EE/CE with 15+ years experience, or Master's with 10-12 years, or PhD with 8-10 years.
• Proven track record as a chip lead for complex SoC/ASIC programs from architecture through productization.
• Deep expertise in high-speed mixed-signal SoC design, SerDes (100G+/lane), and advanced CMOS process nodes (5nm, 3nm).
• Strong proficiency in the full ASIC design flow: micro-architecture, RTL, synthesis, DFT, PD, and STA.
• Experience leading silicon bring-up and validation across globally distributed teams.
• Must be eligible to access export-controlled information under U.S. export control laws (EAR).

Nice to have

• Familiarity with optical DSP, coherent or direct-detect transceiver architectures, or high-speed retimers.
• Experience with eAVS (Adaptive Voltage Scaling) or similar power optimization subsystems.
• Knowledge of Silicon Photonics (SiPho) integration and module-level validation.
• Experience working in a multi-site, globally distributed engineering organization.

Culture & Benefits

• Comprehensive benefits focusing on financial well-being, family support, and physical/mental health.
• Employee stock purchase plan with a 2-year look back.
• Robust mental health resources and recognition/service awards.
• Culture of technical rigor, knowledge sharing, and continuous learning.