Назад
Company hidden
14 часов назад

Principal Physical Design/Implementation Engineer (Semiconductor)

154 680 - 231 700$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Релокация
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/

TL;DR

Principal Physical Design/Implementation Engineer (Semiconductor): Driving the RTL-to-GDSII implementation and physical design strategy for complex SubSystems in data infrastructure SoCs with an accent on synthesis, floorplanning, and timing closure. Focus on architecting next-generation physical design methodologies and delivering production-quality designs on advanced process nodes.

Location: Onsite full-time in Santa Clara, CA or Irvine, CA. Relocation is provided.

Salary: $154,680 - $231,700 per annum

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

  • Architect and lead the development of next-generation physical design methodologies and automation flows for complex SubSystems.
  • Drive RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, clock tree synthesis, and timing closure.
  • Perform hands-on hardening of complex subsystems and deliver reference floorplans to SoC teams.
  • Collaborate with DFT and RTL teams to ensure correct insertion and timing closure at the SoC level.
  • Mentor and coach senior and junior engineers to promote technical growth and best practices.
  • Evaluate and drive the adoption of emerging EDA tools in partnership with CAD teams and external vendors.

Requirements

  • Bachelor's degree in CS, Electrical Engineering, or related field with 10-15 years of experience, or Master's/PhD with 5-10 years of experience.
  • Domain expertise in SoC architecture, processor cores, memory, and PCIE/CXL.
  • Extensive experience in synthesis, floorplanning, P&R, and timing closure for large subsystems.
  • Proficiency in Verilog and static quality checks of implemented RTL.
  • Hands-on experience with interpretive languages such as Python or Perl.
  • Must be eligible to access export-controlled information under U.S. law (EAR).

Nice to have

  • Experience with Ethernet, Security, and peripheral interfaces.
  • Experience with memory generation.
  • Experience with leading foundries and latest process nodes (2nm, 3nm, 5nm).

Culture & Benefits

  • Comprehensive benefits focusing on financial well-being, family support, and mental/physical health.
  • Employee stock purchase plan with a 2-year look back.
  • Robust mental health resources and recognition/service awards.
  • Environment dedicated to purposeful and enduring innovation.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →