Design Verification Engineer (ASIC)

Location: San Jose, California, United States; onsite role with legal authorization to work in the US required

Annual base salary: $143,800–$230,000

Company

hirify.global develops SoC and embedded IP products through its ASIC Product Division.

What you will do

• Develop verification environments for SoC subsystems and embedded IP using SystemVerilog and UVM.
• Design UVM agents, behavioral models, coverage models, and assertions.
• Develop randomized and directed test cases against product specifications.
• Analyze and debug simulation failures and coverage results.
• Perform system-level and block-level design verification in collaboration with design and verification teams.
• Analyze and resolve complex verification trade-off scenarios.

Requirements

• Bachelor’s degree in Electrical and Electronic Engineering, Computer Science, or an equivalent field.
• 12+ years of relevant industry experience preferred.
• Experience with system-level and block-level design verification, ASIC verification flows, and design verification methodologies.
• Fluent knowledge of RTL verification methodologies, including SystemVerilog and object-oriented verification languages such as OVM or UVM.
• Working knowledge of C/C++, Perl, and scripting; strong independent design-debugging skills.
• Must have legal authorization to work in the United States.

Nice to have

• Experience with hardware design and debugging, C++/SystemC, emulators, or FPGA-based prototyping.
• Familiarity with chip design methodologies and tools.
• Knowledge of CPU, DDR, bus protocol, network protocol, or DSP design.

Culture & Benefits

• Collaborative work with verification and design teams.
• Discretionary annual bonus and competitive new-hire and annual equity awards.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and Employee Stock Purchase Program.
• Paid holidays, sick leave, vacation time, and applicable family and other leave programs.