обновлено 3 дня назад
Senior Formal Verification Engineer (AI SoC)
220 920 - 311 890$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Formal Verification Engineer (AI SoC): Ensuring the functional correctness of complex AI SoC IP blocks and subsystems with an accent on formal verification strategy, SystemVerilog Assertions, exhaustive property coverage, and sign-off. Focus on developing scalable verification environments, analyzing convergence and coverage closure, debugging pre-silicon issues, and improving verification quality through post-silicon validation.
Location: Hybrid role based at an assigned site in the United States, with primary location in Folsom, California and additional locations in Santa Clara, California; Hillsboro, Oregon; and Austin, Texas.
Annual salary range: $220,920–$311,890 USD.
Company
develops processors, AI SoCs, cloud and edge technologies, memory, programmable solutions, and connectivity products.
What you will do
- Own formal verification strategy and execution for complex SoC IP blocks and subsystems.
- Develop formal verification environments with SystemVerilog Assertions, formal tools, properties, constraints, and coverage goals.
- Drive formal sign-off through convergence analysis, coverage closure, and exhaustive verification.
- Collaborate with architects, RTL developers, simulation, physical design, and verification teams to identify corner cases and improve design quality.
- Execute emulation and system simulation models, debug pre-silicon issues, and support chip bring-up and post-silicon analysis.
- Mentor junior engineers, lead technical reviews, and establish reusable verification methodologies.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with 10+ years of related experience.
- 7+ years of ASIC/SoC verification experience, including at least 3+ years focused on formal verification.
- Expertise in formal verification methodologies and tools such as JasperGold, VC Formal, or Questa Formal.
- Strong knowledge of SystemVerilog Assertions, property-based verification, digital design, clock domain crossings, and low-power design.
- Familiarity with UVM-based simulation environments and formal-to-dynamic verification workflows.
- Scripting experience with Python, TCL, or Perl, plus the ability to lead projects and work cross-functionally.
Nice to have
- Experience with security verification activities, functional verification infrastructure, and post-silicon validation.
Culture & Benefits
- Hybrid work model combining on-site work at an assigned site with off-site work.
- Health, retirement, and vacation benefits.
- Competitive pay and stock bonuses.
- Position of Trust requiring consent to and successful completion of an extended background investigation.
- Equal employment consideration and ethical hiring practices without recruitment or employment-related fees.
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