Engineer II - Digital ASIC Design

Location: San Jose, California, United States. The position is performed in the US and requires regular business hours with 70% sitting, 15% standing, and 15% walking. Travel is 0%–25%.

Annual base salary: $70,304–$143,000, plus restricted stock units and quarterly bonuses.

Company

hirify.global is a global semiconductor company developing products and solutions that power technology systems worldwide.

What you will do

• Implement RTL in SystemVerilog for complex digital IP blocks from concept through delivery.
• Optimize power, performance, and area to meet product targets.
• Collaborate with SoC integration and physical design teams on connectivity, timing closure, congestion, and routing issues.
• Lead lint, CDC, RDC, and formal verification activities.
• Verify and validate module and system functionality, including post-silicon bring-up.
• Document design activities and results.

Requirements

• 2.5–5 years of experience in ASIC or FPGA digital design.
• Bachelor’s degree in Electrical Engineering.
• Proficiency in SystemVerilog and synchronous/asynchronous design techniques.
• Experience with Cadence/Synopsys front-end EDA flows, including VCS, SpyGlass, Design Compiler, and PrimeTime.
• Experience writing scripts to improve design efficiency and familiarity with lab equipment such as oscilloscopes and logic analyzers.

Nice to have

• Familiarity with PHY or SerDes protocols.
• Knowledge of IEEE 802.3.

Culture & Benefits

• Health benefits begin on the first day.
• Retirement savings plans and an employee stock purchase program with a two-year lookback feature.
• Employee development and career growth programs.
• Restricted stock units and quarterly bonus payments.