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2 дня назад

ASIC Design Manager

148 900 - 276 500$
Формат работы
onsite
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
ASIC Design Manager (ASIC/RTL/Physical Design): Leading end-to-end digital ASIC development from microarchitecture and RTL through physical implementation, signoff, tapeout, and silicon bring-up with an accent on technical direction, team leadership, and design closure. Focus on resolving timing, power, signal-integrity, IR-drop, electromigration, and package-integration challenges across multidisciplinary engineering teams.

Location: Boulder, CO, United States; listed role locations include Louisville, CO and Beaverton, OR. The position is subject to U.S. export-control requirements: candidates must be U.S. Persons or obtain the required U.S. government export authorizations.

Salary: $148,900–$276,500 annually.

Company

Tektronix, a wholly owned subsidiary of hirify.global, develops precision test and measurement solutions, including instrumentation platforms enabled by custom ASICs.

What you will do

  • Lead, mentor, and grow digital ASIC design, verification, and physical design engineers.
  • Own the ASIC flow from microarchitecture, RTL, and IP integration through synthesis, floorplanning, place-and-route, timing closure, tapeout, and silicon bring-up.
  • Set technical direction across IP, subsystem, full-chip integration, physical implementation, and mixed-signal digital-on-top flows.
  • Drive signoff for timing, signal integrity, power integrity, IR drop, electromigration, formal equivalence, DRC, and LVS.
  • Coordinate architects, UVM verification, DFT, CAD, packaging, validation, product engineering, foundries, vendors, and design-services partners.
  • Manage project plans, resources, costs, milestones, risks, hiring, contractors, and external technical partners.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, a related discipline, or equivalent practical experience.
  • Significant experience developing ASICs or complex digital integrated circuits across design and physical implementation.
  • Experience with microarchitecture, synthesizable SystemVerilog or Verilog RTL, IP integration, synthesis, constraints, and static timing analysis.
  • Experience with physical design activities such as floorplanning, power planning, clock-tree synthesis, place-and-route, timing closure, and physical signoff.
  • Experience supporting ASIC milestones including design closure, tapeout, silicon bring-up, qualification, or production release.
  • Must meet U.S. export-control requirements as a U.S. Person or obtain the necessary government authorization.

Nice to have

  • Formal engineering management experience, including hiring, coaching, career development, and resource planning.
  • Master’s or doctoral degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience with high-speed or mixed-signal ASICs, DSP architectures, data-converter interfaces, or instrumentation.
  • Experience with advanced packaging, chiplets, FPGA prototyping, emulation, foundries, OSAT partners, or EDA suppliers.
  • Experience improving ASIC methodologies, automation, and execution practices.

Culture & Benefits

  • Collaborative, technically rigorous engineering environment focused on innovation and continuous learning.
  • Opportunity to shape ASIC technology direction and next-generation instrumentation platforms.
  • Work with multidisciplinary engineering teams and external technology partners.
  • Equal opportunity employer committed to inclusion, diversity, and reasonable accommodations.

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