обновлено 8 дней назад
Senior Custom ASIC Engineering Lead (AI)
143 800 - 230 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Senior Custom ASIC Engineering Lead (AI): Leading customer ASIC programs from RFQs and technology collateral through design, testing, packaging, fabrication, bring-up, and production with an accent on physical design, STA, DFT, low-power design, and advanced technology-node tape-outs. Focus on analyzing PPA tradeoffs, identifying risks in EDA reports and design flows, and coordinating cross-functional teams to achieve tape-out quality.
Location: San Jose, California, USA
Annual base salary: $143,800–$230,000
Company
develops infrastructure chips that enable customers to produce ASICs across semiconductor industry segments, including AI, HPC, networking, and storage.
What you will do
- Manage external customer ASIC programs from RFQs and technology or IP collateral through design, testing, packaging, fabrication, bring-up, and production.
- Advise customers on EDA tools, design flows, methodologies, and best practices, coordinating Q&A sessions with technology experts.
- Assess design-quality and schedule risks, then coordinate mitigation actions with cross-functional teams.
- Execute physical design flows to verify customer tape-in netlists against tape-out quality standards.
- Track developments in IP, semiconductor technology, and end-user applications.
- Collaborate with marketing, sales, legal, regulatory compliance, and other engineering teams.
Requirements
- Multiple tape-outs using advanced technology nodes.
- Ability to analyze PPA tradeoffs across library components and architectures.
- Knowledge of low-power design and power management.
- Hands-on experience with physical design, STA, EDA tools, design flows, logic simulation, testing, and packaging.
- Programming experience with TCL, shell, and scripting languages.
- Bachelor’s degree with 12+ years of related experience, or master’s degree with 10+ years of related experience.
Nice to have
- Exposure to SERDES communication protocols.
- Experience with logic design, chip architecture, microarchitecture, Verilog RTL coding, front-end logic design verification, DRC, or logic synthesis.
- Knowledge of DFT methods, including scan, memory BIST, and repair.
Culture & Benefits
- Annual discretionary bonus and eligibility for new-hire and annual equity awards.
- Medical, dental, and vision plans.
- 401(k) participation with company matching and an Employee Stock Purchase Program.
- Employee Assistance Program, paid holidays, paid sick leave, vacation, and applicable family and other leave.
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