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ΠΎΠ±Π½ΠΎΠ²Π»Π΅Π½ΠΎ 9 часов Π½Π°Π·Π°Π΄

Senior Custom ASIC Engineering Lead (AI)

143Β 800 - 230Β 000$
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior/lead
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

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TL;DR

Senior Custom ASIC Engineering Lead (AI): Managing external customer ASIC programs from inception to production with an accent on physical design, STA, DFT, and packaging. Focus on proactively assessing design risks, executing physical design flows, and driving cross-functional collaboration to ensure high-quality tape-outs for AI, HPC, and networking applications.

Location: Must be based in the USA (San Jose, CA)

Salary: $143,800 - $230,000

Company

hirify.global is a global technology leader that develops critical infrastructure chips for the semiconductor industry.

What you will do

  • Manage end-to-end customer ASIC programs including RFQs, design, fabrication, and production.
  • Advise customers on EDA best practices and design methodologies.
  • Proactively assess and mitigate risks to design quality and project schedules.
  • Execute physical design flows to ensure netlists meet stringent quality standards.
  • Collaborate with marketing, sales, and regulatory teams regarding chip specifications.
  • Stay updated on hirify.global IP, technology, and end-user application developments.

Requirements

  • Must be authorized to work in the USA
  • 12+ years of experience with a Bachelor's degree or 10+ years with a Master's degree.
  • Proven track record of multiple tape-outs in advanced technology nodes.
  • Hands-on experience in physical design, STA, EDA tools, and logic simulation.
  • Proficiency in TCL, shell, and scripting languages.
  • Knowledge of low power design and power management.

Nice to have

  • Experience with SERDES communications protocols.
  • Knowledge of logic design, chip architecture, and microarchitecture.
  • Familiarity with Verilog RTL coding and logic synthesis.
  • Experience with DFT methods including scan and memory BIST.

Culture & Benefits

  • Comprehensive medical, dental, and vision insurance plans.
  • 401(k) participation with company matching.
  • Employee Stock Purchase Program (ESPP) and equity awards.
  • Paid holidays, sick leave, and vacation time.
  • Support for Paid Family Leave and other leaves of absence.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’