Senior Staff Integration Design Engineer (FPGA)

Location: San Jose, CA, United States; onsite office role. Candidates must provide satisfactory proof of their right to work in the United States.

Base pay: $220,800 annually. Additional variable or incentive compensation and equity may be available.

Company

hirify.global develops low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices, for customers worldwide.

What you will do

• Integrate IP blocks, including DDR PHY, into shared HPIO sectors and full-chip FPGA views using digital and custom design flows.
• Create and maintain sector-level SDC constraints, reconcile clock and constraint conflicts, and support STA sign-off.
• Run RTL, synthesis, logical equivalence checking, static timing analysis, DFT scan integration, and related implementation flows.
• Support custom and physical design integration, including custom cell reuse, SPEF extraction, dummy fill, and clock-critical routing reviews before tapeout.
• Run design verification regressions, manage version-controlled sector releases, and track issues, schedules, and release notes in JIRA.
• Build and validate full-chip power models, characterize power across process, voltage, and temperature corners, and correlate simulations with silicon and production test data.

Requirements

• BS or MS degree in Electronics, Computer, or Electrical Engineering.
• 15+ years of experience in ASIC, SoC, or FPGA design and product development.
• In-depth experience with custom and digital design implementation for IP or sector integration; Verilog and SystemVerilog expertise is required.
• Expertise in RTL coding and verification, synthesis, equivalence checking, SDC, DFT, and ATPG flows.
• Knowledge of semiconductor principles, transistor-level analysis, Cadence Virtuoso, SPICE-class simulation, CMOS low-power concepts, and power correlation to silicon measurements.
• Strong coding and scripting skills in tools such as Perl, Tcl, Shell, SKILL, or Python, plus communication across design, test, DFT, verification, and product engineering teams.

Nice to have

• FPGA or CPLD design and integration experience.
• IP and full-chip functional verification experience.
• Project leadership across planning, resourcing, tapeout, silicon characterization, and validation.
• Experience with multiple process nodes or foundries, such as TSMC or Samsung.

Culture & Benefits

• Fast-paced, results-oriented environment with a team-first working style.
• Collaboration across international engineering, manufacturing, sales, marketing, and support functions.
• Comprehensive benefits may include healthcare, retirement plans, paid time off, and other benefits.
• Employment is subject to successful background and reference checks.
• Lattice is an E-Verify employer and requires Form I-9 employment eligibility verification upon hire.