Principal Engineer - Design For Test (DFT)

TL;DR

Principal Engineer - Design For Test (DFT) (ASIC): Implementing DFT and Test architectures on complex IP and SoC for custom compute ASIC designs with an accent on chiplet solutions and Tessent tools. Focus on running Tessent SSN, performing verification and debug, and mentoring a team of DFT engineers.

Location: Morrisville, NC, USA

Salary: $160,400 – $237,320 per annum

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Implement DFT/Test on complex IP and SOC for multiple custom/compute ASIC designs.
• Run Tessent tools for insertion of all DFT structures, including chiplet DFT solutions and Tessent SSN.
• Collaborate with leads to define Design-for-Test architecture and implement additional DFT/DFX features.
• Handle STA constraint definition, pattern generation, and post-silicon bring-up and debug.
• Mentor, guide, and drive a small team of DFT engineers.
• Work to enhance DFT methodologies and tools.

Requirements

• Bachelor’s, Master’s or PhD in Computer Science, Electrical Engineering or related fields.
• Minimum 10 years of work experience, with at least 8 years specifically in the custom chip (ASIC) design business.
• Hands-on experience in SCAN, MBIST, Validation, STA, IP-DFX, and post-silicon bring-up/debug.
• Thorough knowledge of DFT/Test architecture solutions for 2.5D/3D IC design.
• Experience with Siemens/Synopsys Tool set, specifically Tessent.
• Must be eligible to access export-controlled information under U.S. export control laws (EAR).

Nice to have

• Scripting skills using Python, PERL, Tcl, and C-Shell.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards for contributions and milestones.