Physical Design Engineer (Core IP)

TL;DR

Physical Design Engineer (Core IP): Performing physical design implementation of custom CPU designs from RTL to GDS with an accent on synthesis, place and route, and static timing analysis. Focus on optimizing power, frequency, and area for high-performance compute processors across client, server, and AI segments.

Location: On-site in Hillsboro, Oregon, USA

Salary: $122,440–$232,190 USD

Company

hirify.global is a global leader in semiconductor technology, driving innovations in AI, cloud-to-edge computing, and microprocessor architecture.

What you will do

• Execute physical design implementation of custom CPU designs from RTL to GDS.
• Conduct synthesis, place and route, clock tree synthesis, and floor planning.
• Perform static timing analysis, power/clock distribution, and reliability verification.
• Execute signoff tasks including formal equivalence, DRC/LVS, and noise analysis.
• Collaborate with logic, circuit, and architecture teams to improve CPU microarchitectures.
• Work with EDA vendors to enhance tool capabilities for high-speed, low-power CPU design.

Requirements

• Must be based in or able to work on-site in Hillsboro, Oregon.
• Bachelors or Masters in Computer or Electrical Engineering.
• 3+ years of relevant experience (with Bachelors) or 2+ years (with Masters).
• 2+ years of experience in digital logic block synthesis.
• Proficiency in integrated circuit design tools like Synopsys or Cadence.
• Experience with scripting in TCL and at least one other language (Python, Perl, or Ruby).

Culture & Benefits

• Competitive total compensation package including pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Opportunity to work on cutting-edge microprocessor architecture.
• Collaborative environment focused on global technological innovation.