Principal Engineer, Digital IC Design (SoC)

TL;DR

Principal Engineer, Digital IC Design (SoC): Integrating internal and external IP blocks at the chip level with an accent on SoC integration, RTL design, and timing closure. Focus on driving complex SoC designs from initial stages to tape-out, ensuring zero-defect products through rigorous verification and static checks.

Location: Santa Clara, CA, USA

Salary: $158,600 - $237,600 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Integrate internal and external IP blocks at the chip level within the SoC Integration team.
• Take full ownership of SoC design portions, driving them from initial stages to completion.
• Collaborate on floorplanning and the interconnection of IP blocks.
• Perform static checks and drive timing closure to ensure high-quality tape-outs.
• Run functional simulations, gate-level simulations, and CDC using industry-standard EDA tools.
• Mentor and provide technical guidance to junior engineers.

Requirements

• Bachelor's degree in EE or Computer Engineering (10-15 years exp) or Master's/PhD (5-10 years exp).
• Proven track record of taping out complex SoCs and performing post-silicon debug.
• Strong RTL design skills using SystemVerilog.
• Expertise in SoC integration, clock/reset design, CDC, and timing constraints.
• Knowledge of ARM protocols (APB, AHB, AXI, CHI) and NOC architectures.
• Must be eligible to access export-controlled information under U.S. law.

Nice to have

• Proficiency in scripting languages such as Python or Tcl.
• Experience utilizing AI tools to enhance development workflows.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate contributions and milestones.