Principal Static Timing Analysis Engineer

TL;DR

Principal Static Timing Analysis Engineer (Wireless SoCs): Develop timing constraints and signoff for low-power multi-core SoCs supporting wireless protocols, sensor hubs, and AI/ML with an accent on complex gated clock networks and asynchronous sources. Focus on evolving STA flows, scripting analysis for rapid closure, and mixed-signal IP integration.

Location: Austin, TX (Hybrid)

Salary: $160,650 - $298,350 USD

Company

Leading innovator in low-power wireless connectivity, building highly integrated SoCs for smart home, industrial IoT, and smart cities markets.

What you will do

• Develop timing constraints at IP and SoC levels in collaboration with designers.
• Improve static timing analysis flows and methodologies.
• Define timing signoff criteria including aging, on-chip variation, and signal integrity.
• Analyze timing reports using scripting to drive rapid closure.
• Collaborate with global design team to resolve complex timing issues.
• Drive timing closure for mixed-signal IP integration with multi-functional team.

Requirements

• 15+ years in industry.
• Bachelor’s or Master’s in Electrical or Computer Engineering.
• In-depth knowledge of timing closure flow and methodology.
• Experience in timing constraint development for functional and test modes (e.g., scan).
• Hands-on with static timing tools like Tempus or Primetime.
• Scripting in Perl, Python, Tcl, shell; knowledge of low-power design, timing models, and design flows (Lint, CDC, Synthesis, etc.).
• Verilog and SystemVerilog; experience with AI-powered tools.

Culture & Benefits

• Competitive medical (PPO or HSA), dental, vision plans.
• 401k with match, Roth option, equity (RSUs), life/disability coverage.
• Flexible spending accounts, adoption assistance, back-up childcare.
• Flexible PTO, 3 paid volunteer days, charitable match, tuition reimbursement.
• Free downtown parking, onsite gym, wellness offerings, free snacks.