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Staff Digital Design Engineer (SoC Low Power, Clocking & Integration)

150 500 - 279 500$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Staff Digital Design Engineer (SoC Low Power, Clocking & Integration) (Wireless MCU SoCs): Developing and integrating highly integrated, low-power SoCs for wireless IoT applications with an accent on power intent, clocking infrastructure, RTL design, and subsystem integration. Focus on designing power and clock domains, integrating processors and IPs, debugging CDC/RDC and protocol issues, and validating silicon bring-up.

Location: Austin, TX; hybrid work

Annualized base pay: $150,500–$279,500 USD. Additional compensation may include an annual cash bonus, equity package, and benefits.

Company

hirify.global develops low-power wireless connectivity and highly integrated SoCs for smart home, industrial IoT, and smart cities applications.

What you will do

  • Develop complex SoC architectures with multiple processors, digital and mixed-signal subsystems, power domains, and clock domains optimized for customer power scenarios.
  • Define and implement SoC low-power architecture, including power domains, retention, isolation, level shifters, sequencing, and UPF/CPF power intent.
  • Design and integrate clock-generation, distribution, gating, muxing, reset, monitoring, and power-management infrastructure.
  • Architect and integrate SoC interconnects and bus fabrics using AXI, AHB, APB, and related protocols.
  • Lead small teams designing and verifying digital subsystems, and drive architecture, design, and verification reviews.
  • Analyze and debug low-power, clocking, CDC/RDC, integration, and protocol issues through simulation, emulation, synthesis, and silicon bring-up.

Requirements

  • BS or MS in Electrical Engineering and 10–20 years of professional experience in digital CMOS IC design.
  • Ability to lead small teams designing complex digital subsystems and deliver high output independently.
  • Strong RTL design expertise with Verilog and SystemVerilog.
  • Strong knowledge of SoC clocking, CDC, RDC, synchronization, reset architectures, and timing.
  • Extensive low-power design experience with UPF, power gating, retention, isolation, level shifting, and power-aware verification.
  • Experience with AXI, AHB, APB, interconnect architectures, complex subsystem integration, processor clusters, memory subsystems, and third-party IP.
  • Knowledge of embedded processor systems and C coding; experience with RTL and gate-level simulation, waveform analysis, power analysis, synthesis, and timing constraints.
  • Experience optimizing designs for power, performance, and area with backend teams, and integrating analog and mixed-signal subsystems.
  • Experience with scripting and automation using Python, Perl, or Tcl; revision control and configuration management with tools such as Perforce, Git, or Methodics.
  • Excellent written and verbal communication skills.
  • Experience with AI-powered tools and technologies for productivity, analysis, and decision-making.

Culture & Benefits

  • Hybrid work environment with onsite facilities including downtown parking and a gym.
  • Medical, dental, vision, HSA, flexible spending, life, disability, and adoption benefits.
  • 401(k) matching, Roth plan option, equity rewards, and competitive base pay.
  • Flexible PTO, three paid volunteer days annually, charitable contribution matching, and tuition reimbursement.
  • Additional commuter, legal, and pet insurance benefits, plus backup childcare and wellness offerings.

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