Principle VLSI/ASIC Design Engineer

Location: Hybrid in Sunnyvale, California, United States of America; work from an HPE office an average of 2 days per week.

Salary: USD 174,000–352,500 annual base salary in California; variable incentives may also be offered.

Company

Global edge-to-cloud technology organization developing solutions that connect, protect, analyze, and manage data and applications from edge to cloud.

What you will do

• Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications.
• Define architectures, microarchitectures, design methodologies, and implementation plans aligned with product requirements and technology roadmaps.
• Design and modify complex RTL blocks and drive implementation through synthesis, timing analysis, physical implementation support, and production readiness.
• Evaluate performance, power, area, scalability, reliability, cost, risk, and schedule through modeling, simulation, prototyping, and experimental analysis.
• Conduct design reviews, develop integration plans, and contribute to ASIC architectures, methodologies, standards, and technology adoption.
• Collaborate with architecture, hardware, firmware, verification, physical design, systems, software, manufacturing, suppliers, and external development teams; provide technical leadership and mentor engineers.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent experience may be considered.
• Typically 9 or more years of experience in ASIC, VLSI, SoC, or related hardware design.
• Experience designing complex RTL blocks for networking, compute, communications, storage, or other advanced SoC applications.
• Experience leading architecture and design exploration through RTL implementation and product integration.
• Advanced knowledge of ASIC and VLSI design principles, digital logic, RTL design, and SoC development.
• Proven experience developing complex RTL with Verilog, SystemVerilog, or comparable hardware description languages.
• Understanding of ASIC development flows, including architecture, microarchitecture, RTL coding, synthesis, timing analysis, physical design interaction, and design signoff.
• Experience with design modeling, simulation, performance analysis, empirical evaluation, design methodologies, tools, automation, and engineering practices.
• Strong analytical, problem-solving, technical decision-making, written, verbal, collaboration, and communication skills, including the ability to explain complex concepts to technical and executive audiences.
• Ability to evaluate design alternatives, communicate architectural proposals and tradeoffs, influence decisions across functions and business units, and mentor engineers without direct management responsibility.

Nice to have

• Design verification experience.
• Experience with networking ASICs, data-processing units, switching, routing, acceleration, storage, or high-performance computing architectures.
• Experience with high-speed interfaces, packet-processing pipelines, memory subsystems, interconnects, or performance-critical datapaths.
• Familiarity with formal verification, constrained-random verification, coverage methodologies, or verification planning.
• Experience with low-power design, clock-domain crossing, reset-domain crossing, DFT, and design-for-reuse methodologies.
• Knowledge of industry standards and leading-edge ASIC implementation technologies.
• Experience working with outsourced development partners, IP vendors, foundries, or semiconductor suppliers.

Culture & Benefits

• Hybrid work model with flexibility to manage work and personal needs.
• Health, financial, and emotional wellbeing benefits for employees and their loved ones.
• Personal and professional development programs supporting career growth and expertise development.
• Inclusive workplace that values varied backgrounds and individual uniqueness.