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Technical Staff Engineer - Design Implementation (SoC)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Technical Staff Engineer - Design Implementation (SoC): Developing scalable RTL-to-silicon methodologies and implementation flows for next-generation 12nm hierarchical SoCs with an accent on timing convergence, low-power design, and multi-die integration. Focus on defining timing constraints, evaluating design partitioning, driving floorplanning and clock-tree decisions, and mentoring engineers on implementation best practices.

Location: Chandler, Arizona, United States; onsite. Travel: 0%–25%.

Company

hirify.global is a global technology organization developing products and solutions that power electronic systems, with a 17,000-member workforce and a focus on employee development, innovation, and values-based decision-making.

What you will do

  • Develop and deploy SoC implementation flows for complex chips, including hierarchical design planning, logic synthesis, timing closure, power analysis, UPF specification, and low-power implementation.
  • Define top-level timing methodologies across IPs, subsystems, and full-chip integration to achieve predictable signoff convergence.
  • Drive implementation methodology for multi-die integration, timing-constraint strategy, and integration flows.
  • Evaluate design partitioning decisions for their impact on implementation complexity, timing closure, power, yield, and scalability.
  • Develop clock definitions, timing exceptions, interface budgets, and other constraints; collaborate with physical design teams on floorplanning and clock-tree constraints.
  • Mentor engineers on implementation flows, timing-closure strategies, and multi-die design practices.

Requirements

  • BS or MS degree in Electrical Engineering or a related field and 14+ years of experience in SoC implementation activities.
  • Strong hands-on expertise in synthesis, UPF specification, timing closure, hierarchical implementation, and low-power digital design flows.
  • Hands-on experience with industry-standard EDA tools: Genus, iSpatial, Design Compiler, Fusion Compiler, Tempus, PrimeTime, PrimePower, VCLP, RTL Architect, Conformal, and Formality.
  • Deep understanding of SoC timing architecture, including clocking strategy, constraint development, timing budgeting, and block-to-top convergence.
  • Ability to incorporate system-level timing specifications into implementation constraints for synthesis and timing closure.
  • Good background in digital microarchitecture, RTL coding, and front-end-to-implementation handoff quality.
  • Strong cross-functional communication skills and demonstrated technical leadership in ambiguous environments.
  • Ability to build new process flows and scale implementation methodologies across teams, proactively developing methodologies when existing flows do not scale.
  • Experience in first-generation product environments where flows, margins, and best practices must be established.

Culture & Benefits

  • Values-based workplace emphasizing trust, empowerment, respect, diversity, communication, and community.
  • Opportunities for employee development through leadership and career-growth programs.
  • Full-time employment with a global technology organization.
  • Physical requirements include approximately 80% sitting, 10% standing, and 10% walking, with hearing, seeing, and talking required.

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