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Senior Principal Engineer, Physical Designer (ASIC)

177 820 - 266 400$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Principal Engineer, Physical Designer (ASIC): Leading RTL-to-GDSII implementation and physical design methodology for next-generation, high-performance processor chips with an accent on hierarchical SoC design, advanced process nodes, and tapeout execution. Focus on shaping physical design infrastructure, driving timing and power integrity signoff, developing automation flows, and leading cross-functional engineering teams.

Location: Santa Clara, CA, United States

Expected base pay: $177,820–$266,400 per annum

Company

hirify.global develops semiconductor solutions and custom Processor/ASIC products for enterprise, cloud, AI, server, and networking infrastructure.

What you will do

  • Shape the long-term vision for physical design capabilities, infrastructure, methodologies, flows, and automation.
  • Lead RTL-to-GDSII implementation for multiple SoC programs, including synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power and signal integrity signoff, and DRC/LVS verification.
  • Provide technical direction for physical design teams and deliver complex, high-performance SoC tapeouts on schedule.
  • Lead cross-functional collaboration with design teams, influence design decisions, and resolve conflicts.
  • Build and retain a high-performing organization through team structure, hiring, performance management, mentoring, and career development.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 15+ years of related experience; or a Master’s degree with 10–12 years; or a PhD with 8–10 years; equivalent professional experience may substitute for a degree.
  • 15+ years of progressive back-end physical design and verification experience, including significant leadership responsibilities.
  • Experience leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules.
  • Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges.
  • In-depth understanding of current design technologies used in major foundries and modern EDA tools and flows.
  • Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure.
  • Automation and scripting proficiency with Makefile, Tcl, Python, or Perl.
  • Strong communication and collaboration skills, including the ability to influence cross-functional teams and executive stakeholders.
  • Experience developing and deploying advanced physical design methodologies and flows.

Nice to have

  • Knowledge of static timing analysis tools such as PrimeTime and Tempus; EM/IR-drop and crosstalk analysis tools such as PTSI, Voltus, RedHawk, and PrimeRail; extraction tools such as Quantus and StarRC; and formal or physical verification tools such as Formality, Verplex, Calibre, and Hercules.
  • Familiarity with AI/ML-driven optimization in physical design tools.

Culture & Benefits

  • Full-time employment with bonus and equity plan eligibility, including a new-hire equity grant and annual equity refreshers.
  • Benefits support financial well-being, family support, mental and physical health, and recognition.
  • Benefits include an employee stock purchase plan with a two-year lookback, family support programs, mental health resources, and recognition and service awards.
  • Applicants requiring reasonable accommodation during selection may contact the hirify.global HR Helpdesk.
  • Access to export-controlled technology may require U.S. export license review; applicants must be eligible to access such information under applicable law.
  • AI tools, transcription apps, real-time answer generators, and automated note-taking bots are prohibited during interviews; unauthorized use results in disqualification.

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