Principal Engineer (AMS IP Architecture)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
TL;DR
Principal Engineer (AMS IP Architecture): Defining and driving next-generation analog and mixed-signal IP architectures for high-performance computing and ultra-low power products with an accent on SerDes modeling, DSP algorithm development, and silicon correlation. Focus on architecting end-to-end PCIe Gen7/Gen8 solutions, mitigating margin risks, and ensuring system-level feasibility through cross-functional collaboration.
Location: Must be based in the US (Santa Clara, Phoenix, Folsom, Hillsboro, or Austin) with a hybrid work model.
Salary: $220,920–$311,890 USD
Company
is a global leader in semiconductor technology, building scalable engineering solutions across product enablement, custom silicon, and foundry services.
What you will do
- Architect end-to-end PCIe Gen7/Gen8 SerDes models using MATLAB/Simulink.
- Develop real-time calibration and adaptation DSP algorithms for SerDes equalization.
- Execute link simulations to validate protocol specs and mitigate margin risks prior to tapeout.
- Validate simulation models against lab silicon measurements and resolve discrepancies.
- Collaborate with analog, digital, and hardware teams on circuit trade-offs and lab bringup.
- Perform custom link budget analyses and evaluate early-stage protocol updates.
Requirements
- M.Sc. or Ph.D. in Electrical or Computer Engineering with a focus on high-speed communications or analog circuits.
- Deep expertise in SerDes modeling, high-speed analog CMOS design, or DSP techniques for timing recovery.
- Experience analyzing and closing link budgets for NRZ or PAM4 signaling at 100Gbps+.
- Hands-on experience with SerDes transmitter/receiver architectures and equalization techniques (FFE, DFE, CTLE).
- Ability to correlate models with silicon measurements and debug discrepancies systematically.
- Must be eligible to work in the United States and pass an extended background investigation.
Nice to have
- Familiarity with C, Verilog-A, or SystemVerilog for co-simulation or algorithm prototyping.
Culture & Benefits
- Competitive total compensation package including stock bonuses.
- Comprehensive health, retirement, and vacation benefit programs.
- Hybrid work model allowing flexibility between on-site and off-site work.
- Opportunity to work on cutting-edge architecture within a data-driven engineering organization.
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