3 дня назад
Design Verification Engineer (ASIC)
150 000 - 275 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Design Verification Engineer (ASIC): Developing and maintaining UVM/SystemVerilog-based verification environments for IP subsystems with an accent on PCIe, Ethernet, and CPU interfaces. Focus on driving coverage closure, validating hardware-software stack correctness, and solving complex corner-case verification challenges in a frontier AI hardware startup.
Location: On-site in San Jose, CA
Compensation: $150,000 – $275,000 plus significant equity
Company
is a frontier AI hardware startup building inference-focused chips, racks, and software to redefine infrastructure for the fastest-growing industry in history.
What you will do
- Own end-to-end verification for IP subsystems including PCIe, Ethernet, and CPU architectures.
- Develop and maintain scalable UVM/SystemVerilog-based verification environments.
- Collaborate with internal IP teams and vendors to ensure architecture requirements are met.
- Validate seamless interaction of external IPs within the broader SoC architecture.
- Define verification metrics, analyze coverage gaps, and sign off on complex corner cases.
Requirements
- 5+ years of design verification experience
- Hands-on experience with SystemVerilog and UVM methodologies.
- Proficiency with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
- Ability to thrive in a fast-paced, in-person startup environment.
- Must be able to work on-site in San Jose, CA.
Culture & Benefits
- Comprehensive medical, dental, and vision packages with generous premium coverage.
- Housing subsidy of $2,000 per month for those living within walking distance of the office.
- Relocation support provided for those moving to San Jose.
- Daily lunch and dinner provided in the office.
- Wellness benefits covering fitness and mental health.
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