Photolithography Process Engineer (Semiconductor)

TL;DR

Photolithography Process Engineer (Semiconductor): Managing high-volume wafer manufacturing processes with an accent on lithography equipment optimization and defect reduction. Focus on implementing Six-Sigma statistical methodologies to improve tool availability, process stability, and yield in a complex manufacturing environment.

Location: Chandler, Arizona (Onsite)

Company

hirify.global is a global leader in secure connectivity solutions for embedded applications, driving innovation in the automotive, industrial, and IoT markets.

What you will do

• Optimize photolithography processes to reduce wafer scrap and rework rates.
• Develop and maintain standard operating procedures for Out of Control Action Plans.
• Apply Six-Sigma statistical methodologies to drive process development and optimization.
• Collaborate with equipment and device teams to identify sources of variation and improve integration margins.
• Improve tool utilization and availability through capacity planning and modeling.
• Train technicians and FAB associates on process control and tool operation standards.

Requirements

• BS or MS degree in engineering or a relevant field of study.
• 5+ years of process engineering experience in a high-volume semiconductor manufacturing environment.
• Proficiency in Six-Sigma statistical methodology.
• Experience with semiconductor manufacturing processes is mandatory.
• Ability to work onsite in Chandler, Arizona.

Nice to have

• Experience with ASML Scanners or Canon Steppers.
• Familiarity with TEL ACT 8 or Mark 7 tracks.
• Experience with KLA 8100 CDSEM or Archers.

Culture & Benefits

• Opportunity to work in a high-volume, advanced semiconductor manufacturing environment.
• Commitment to equal opportunity and affirmative action employment.
• Support for reasonable accommodations for qualified individuals.
• Collaborative cross-functional team environment focused on lean manufacturing activities.